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B300D44A102XXG

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BelaSigna 300
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WLCSP Pin Out
A total of 35 active pins are present on BelaSigna 300. They are organized in a staggered array. A description of these pins
is given in Table 5.
Table 5. PAD DESCRIPTIONS
Pad Index BelaSigna 300 Pad Name Description I/O A/D
A1 GNDRCVR Ground for output driver N/A A
A5 VBATRCVR Power supply for output stage I A
B2 RCVR_HP+ Extra output driver pad for high power mode O A
C3 RCVR+ Output from output driver O A
A3 RCVR− Output from output driver O A
B4 RCVR_HP− Extra output driver pad for high power mode O A
B6 CAP0 Charge pump capacitor pin 0 N/A A
C5 CAP1 Charge pump capacitor pin 1 N/A A
A7 VDBL Doubled voltage O A
B8 VBAT Power supply I A
B10 VREG Regulated supply voltage O A
A9 AGND Analog ground N/A A
A11 AI4 Audio signal input 4 I A
B12 AI2/LOUT2 Audio signal input 2/output signal from preamp 2 I/O A
A13 AI1/LOUT1 Audio signal input 1/output signal from preamp 1 I/O A
B14 AI0/LOUT0 Audio signal input 0/output signal from preamp 0 I/O A
D14 GPIO[4]/LSAD[4] General−purpose I/O 4/low speed AD input 4 I/O A/D
E13 GPIO[3]/LSAD[3] General−purpose I/O 3/low speed AD input 3 I/O A/D
C13 GPIO[2]/LSAD[2] General−purpose I/O 2/low speed AD input 2 I/O A/D
D12 GPIO[1]/LSAD[1]/UART−RX General−purpose I/O 1/low speed AD input 1/and UART RX I/O A/D
E11 GPIO[0]/UART−TX General−purpose I/O 0/UART TX I/O A/D
C9 GNDC Digital ground N/A A
C11 SDA (I2C) I2C data I/O D
D10 SCL (I2C) I2C clock I/O D
E9 EXT_CLK External clock input/internal clock output I/O D
D8 VDDC Core logic power O A
E7 SPI_CLK Serial peripheral interface clock O D
C7 SPI_SERI Serial peripheral interface input I D
D6 SPI_CS Serial peripheral interface chip select O D
E5 SPI_SERO Serial peripheral interface output O D
D4 PCM_FR PCM interface frame I/O D
E3 PCM_SERI PCM interface input I D
D2 PCM_SERO PCM interface output O D
C1 PCM_CLK PCM interface clock I/O D
E1 Reserved Reserved
BelaSigna 300
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Assembly / Design Notes
For PCB manufacture with BelaSigna 300,
ON Semiconductor recommends solder−on−pad (SoP)
surface finish. With SoP, the solder mask opening should be
non−solder mask−defined (NSMD) and copper pad
geometry will be dictated by the PCB vendor’s design
requirements.
Alternative surface finishes are ENiG and OSP; volume
of screened solder paste (#5) should be less than
0.0008 mm
3
. If no pre−screening of solder paste is used,
then following conditions must be met:
1. the solder mask opening should be >0.3 mm in
diameter,
2. the copper pad will have 0.25 mm diameter, and
3. soldermask thickness should be less than 1 mil
thick above the copper surface.
ON Semiconductor can provide BelaSigna 300 WLCSP
land pattern CAD files to assist your PCB design upon
request.
WLCSP Weight
BelaSigna 300 has an average weight of 0.095 grams.
Recommended Circuit Design Guidelines
BelaSigna 300 is designed to allow both digital and analog
processing in a single system. Due to the mixed−signal
nature of this system, the careful design of the printed circuit
board (PCB) layout is critical to maintain the high audio
fidelity of BelaSigna 300. To avoid coupling noise into the
audio signal path, keep the digital traces away from the
analog traces. To avoid electrical feedback coupling, isolate
the input traces from the output traces.
Recommended Ground Design Strategy
The ground plane should be partitioned into two: the
analog ground plane (AGND) and the digital ground plane
(DGND). These two planes should be connected together at
a single point, known as the star point. The star point should
be located at the ground terminal of a capacitor on the output
of the power regulator as illustrated in Figure 1.
Figure 1. Schematic of Ground Scheme
BelaSigna 300
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The DGND plane is used as the ground return for digital
circuits and should be placed under digital circuits. The
AGND plane should be kept as noise−free as possible. It is
used as the ground return for analog circuits and it should
surround analog components and pins. It should not be
connected to or placed under any noisy circuits such as RF
chips, switching supplies or digital pads of BelaSigna 300
itself. Analog ground returns associated with the audio
output stage should connect back to the star point on separate
individual traces.
For details on which signals require special design
consideration, see Table 6 and Table 7.
In some designs, space constraints may make separate
ground planes impractical. In this case a star configuration
strategy should be used. Each analog ground return should
connect to the star point with separate traces.
Internal Power Supplies
Power management circuitry in BelaSigna 300 generates
separate digital (VDDC) and analog (VREG, VDBL)
regulated supplies. Each supply requires an external
decoupling capacitor, even if the supply is not used
externally. Decoupling capacitors should be placed as close
as possible to the power pads. The VDDC internal regulator
is a programmable power supply that allows the selection of
the lowest digital supply depending on the clock frequency
at which BelaSigna 300 will operate. See the Internal Digital
Supply Voltage section for more details on VDDC.
Two other supply pins are also available on BelaSigna 300
(VDDO and VDDO_SPI) which are internally connected to
the VBAT pin.
Further details on these critical signals are provided in
Table 6. Non−critical signals are outlined in Table 7.
Table 6. CRITICAL SIGNALS
Pin Name Description Routing Guideline
VBAT Power supply
Place 1 mF (min) decoupling capacitor close to pin.
Connect negative terminal of capacitor to DGND plane.
VREG, VDBL Internal regulator for
analog sections
Place separate 1 mF decoupling capacitors close to each pin.
Connect negative capacitor terminal to AGND.
Keep away from digital traces and output traces.
VREG may be used to generate microphone bias.
VDBL shall not be used to supply external circuitry.
AGND Analog ground return Connect to AGND plane.
VDDC Internal regulator for digital core
Place 10 mF decoupling capacitor close to pin.
Connect negative terminal of capacitor to DGND.
GNDC Digital ground return Connect to digital ground.
AI0/LOUT0,
AI1/LOUT1,
AI2/LOUT2
Audio inputs Keep as short as possible.
Keep away from all digital traces and audio outputs.
Avoid routing in parallel with other traces.
Connect unused inputs to AGND.
RCVR+, RCVR−,
RCVR_HP+,
RCVR_HP−
Direct digital audio output Keep away from analog traces, particularly audio inputs.
Corresponding traces should be of approximately the same length.
Ideally, route lines parallel to each other.
GNDRCVR Output stage ground return Connect to star point.
Keep away from all analog audio inputs.
EXT_CLK External clock input / internal
clock output
Minimize trace length. Keep away from analog signals. If possible, sur-
round with digital ground.
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B300D44A102XXG

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Audio DSPs BELASIGNA 300
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