1. General description
The SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data, and vice versa. The UART can handle serial data rates up to
5 Mbit/s.
The SC16C2552B is pin compatible with the PC16552 and ST16C2552. The
SC16C2552B provides enhanced UART functions with 16-byte FIFOs, modem control
interface, DMA mode data transfer and concurrent writes to control registers of both
channels. The DMA mode data transfer is controlled by the FIFO trigger levels and the
RXRDY and TXRDY signals. On-board status registers provide the user with error
indications and operational status. System interrupts and modem control features may be
tailored by software to meet specific user requirements. An internal loopback capability
allows on-board diagnostics. Independent programmable baud rate generators are
provided to select transmit and receive baud rates.
The SC16C2552B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in a plastic PLCC44 package.
2. Features
n Industrial temperature range (40 °C to +85 °C)
n 5 V, 3.3 V and 2.5 V operation
n Pin-to-pin compatible to PC16C552, ST16C2552
n Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
n 5 V tolerant on input only pins
1
n 16-byte transmit FIFO
n 16-byte receive FIFO with error flags
n Independent transmit and receive UART control
n Four selectable receive FIFO interrupt trigger levels; fixed transmit FIFO interrupt
trigger level
n Modem control functions (CTS, RTS, DSR, DTR, RI, CD)
n DMA operation and DMA monitoring via package I/O pins, TXRDY/RXRDY
n UART internal register sections A and B may be written to concurrently
n Multi-function output allows more package functions with fewer I/O pins
n Programmable character lengths (5, 6, 7, 8), with even, odd, or no parity
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte
FIFOs
Rev. 03 — 12 February 2009 Product data sheet
1. For data bus pins D7 to D0, see Table 23 “Limiting values”.
SC16C2552B_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 12 February 2009 2 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
3. Ordering information
4. Block diagram
Table 1. Ordering information
Type number Package
Name Description Version
SC16C2552BIA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
Fig 1. Block diagram of SC16C2552B
TXA, TXB
RXA, RXB
SC16C2552B
XTAL2XTAL1
D0 to D7
IOR
IOW
RESET
002aaa487
DATA BUS
AND
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
A0 to A2
CS
CHSEL
INTERRUPT
CONTROL
LOGIC
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
CLOCK AND
BAUD RATE
GENERATOR
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
MODEM
CONTROL
LOGIC
DTRA, DTRB
RTSA, RTSB
MFA, MFB
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTERS
TRANSMIT
SHIFT
REGISTER
TRANSMIT
FIFO
REGISTERS
SC16C2552B_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 12 February 2009 3 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 2. Pin configuration for PLCC44
D5
D6
D7
A0
XTAL1
SC16C2552BIA44
RXA
TXA
DTRA
RTSA
MFA
GND INTA
XTAL2 V
CC
A1 TXRDYB
A2 RIB
CHSEL CDB
INTB DSRB
CS D4
MFB D3
IOW D2
RESET D1
GND D0
RTSB TXRDYA
IOR V
CC
RXB RIA
TXB CDA
DTRB DSRA
CTSB CTSA
002aaa488
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
Table 2. Pin description
Symbol Pin Type Description
A0 10 I Register select. A0 to A2 are used during read and write operations to select the UART
register to read from or write to.
A1 14 I
A2 15 I
CDA42ICarrier detect A, B (active LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been detected by the
modem for that channel.
CDB 30 I
CHSEL 16 I Channel select. UART channel A or B is selected by the logic state of this pin when
CS is a
logic 0. A logic 0 on CHSEL selects the UART channel B, while a logic 1 selects UART
channel A. Bit 0 of AFR register can temporarily override CHSEL function, allowing user to
write to both channel registers simultaneously with one write cycle.
CTSA 40 I Clear to Send A, B (active LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on the
CTSn pin indicates the modem or data set is ready to
accept transmit data from the SC16C2552B. Status can be tested by reading MSR[4].
CTSB 28 I
CS 18 I Chip select (active LOW). This function selects channel A or channel B in accordance with
the logical state of the CHSEL pin. This allows data to be transferred between the user CPU
and the SC16C2552B.

SC16C2552BIA44,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 2CH
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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