SC16C2552BIA44,518 Datasheet SC16C2552BIA44,518, SC16C2552BIA44,512, SC16C2552BIA44,529 | P13-P15

Product data sheet Rev. 03 — 12 February 2009 13 of 38

NXP Semiconductors

SC16C2552B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR register or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2552B in the FIFO polled

mode of operation. In this mode, interrupts are not generated and the user must poll the

LSR register for TX and/or RX data status. Since the receiver and transmitter have

separate bits in the LSR either or both can be used in the polled mode by selecting

respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

Product data sheet Rev. 03 — 12 February 2009 14 of 38

NXP Semiconductors

SC16C2552B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation and is similar to

the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty

transmit space is available in the Transmit Holding Register (THR). Receive Ready

(RXRDY) at the MFn pin will go to a logic 0 whenever the Receive Holding Register (RHR)

is loaded with a character and AFR[2:1] is set to the RXRDY mode.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO has at least one empty location. TXRDY remains a logic 0 as long as

one empty FIFO location is available. The receive interrupt is set when the receive FIFO

ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll regardless of the

programmed level until the FIFO is full. RXRDY at the MFn pin remains a logic 0 as long

as the FIFO ﬁll level is above the programmed trigger level, and AFR[2:1] is set to the

RXRDY mode.

7.3.2 FIFO mode

Table 8. FIFO Control Register bits description

Bit Symbol Description

7:6 FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to

Table 9.

5:4 FCR[5:4] Not used; initialized to logic 0.

3 FCR[3] DMA mode select.

logic 0 = set DMA mode ‘0’ (normal default condition)

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C2552B is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there

are no characters in the transmit FIFO or Transmit Holding Register, the

TXRDYn pin will be a logic 0. Once active, the TXRDYn pin will go to a

logic 1 after the ﬁrst character is loaded into the Transmit Holding

Receive operation in mode ‘0’: When the SC16C2552B is in 16C450

mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and

there is at least one character in the receive FIFO, the

RXRDY signal at

the

MFn pin will be a logic 0. Once active, the RXRDY signal at the

MFn pin will go to a logic 1 when there are no more characters in the

receiver. Note that the AFR register must be set to the RXRDY mode

prior to any possible reading of the

RXRDY signal.

Product data sheet Rev. 03 — 12 February 2009 15 of 38

NXP Semiconductors

SC16C2552B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

(continued)

Transmit operation in mode ‘1’: When the SC16C2552B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1), the

TXRDYn pin will be a

logic 1 when the transmit FIFO is completely full. It will be a logic 0 if

one or more FIFO locations are empty.

Receive operation in mode ‘1’: When the SC16C2552B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been

reached, or a Receive Time-out has occurred, the

RXRDY signal at the

MFn pin will go to a logic 0. Once activated, it will go to a logic 1 after

there are no more characters in the FIFO. Note that the AFR register

must be set to the RXRDY mode prior to any possible reading of the

RXRDY signal.

2 FCR[2] XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the Transmit Shift Register is not cleared or altered).

This bit will return to a logic 0 after clearing the FIFO.

1 FCR[1] RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the Receive Shift Register is not cleared or altered).

This bit will return to a logic 0 after clearing the FIFO.

0 FCR[0] FIFOs enabled.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to or they will not be

programmed.

Table 9. RCVR trigger levels

FCR[7] FCR[6] RX FIFO trigger level

0001

0104

1008

1114

Table 8. FIFO Control Register bits description

…continued

Bit Symbol Description

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P38

SC16C2552BIA44,518

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Manufacturer:

NXP Semiconductors

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UART Interface IC 16CB 2.5V-5V 2CH

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SC16C2552BIA44,518

SC16C2552BIA44,518

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