SC16C2552B_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 12 February 2009 12 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 through D0)
to the TSR and UART via the THR, providing that the THR is empty. The THR empty flag
in the LSR[5] register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2552B and
receive FIFO by reading the RHR register. The receive section provides a mechanism to
prevent false starts. On the falling edge of a start or false start bit, an internal receiver
counter starts counting clocks at the 16× clock rate. After 7
1
⁄
2
clocks, the start bit time
should be shifted to the center of the start bit. At this time the start bit is sampled, and if it
is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver
from assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 7. Interrupt Enable Register bits description
Bit Symbol Description
7:4 IER[7:4] not used; initialized to logic 0
3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a
modem status change as reflected in MSR[3:0].
logic 0 = disable the Modem Status Register interrupt (normal default
condition)
logic 1 = enable the Modem Status Register interrupt
2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1 IER[1] Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will be
issued whenever the THR is empty and is associated with LSR[5]. In the FIFO
modes, this interrupt will be issued whenever the FIFO and THR are empty.
logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt
(normal default condition)
logic 1 = enable the TXRDY (ISR level 3) interrupt
0 IER[0] Receive Holding Register. In the 16C450 mode, this interrupt will be issued
when the RHR has data, or is cleared when the RHR is empty. In the FIFO
mode, this interrupt will be issued when the FIFO has reached the
programmed trigger level or is cleared when the FIFO drops below the trigger
level.
logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal
default condition)
logic 1 = enable the RXRDY (ISR level 2) interrupt
