SC16C2552B_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 12 February 2009 25 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency =
[3] RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.
[4] Reset pulse must happen when these signals are inactive: CS, IOW, IOR.
10.1 Timing diagrams
t
28d
delay from start to reset
TXRDY
[3]
-8T
RCLK
-8T
RCLK
-8T
RCLK
s
t
RESET
RESET pulse width
[4]
200 - 40 - 40 - ns
N baud rate divisor 1 (2
16
− 1)1(2
16
− 1) 1 (2
16
− 1)
Table 25. Dynamic characteristics
…continued
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
±
10 %; unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
1
t
wclk()
---------------
Fig 5. General write timing
data
active
active
valid
address
002aaa128
A0 to A2
CS
IOW
D0 to D7
t
16s
t
16h
t
13d
t
13w
t
15d
t
6h
t
13h
t
6s
CHSEL
