SC16C2552BIA44,518

SC16C2552B_3 © NXP B.V. 2009. All rights reserved.

The SC16C2552B provides two sets of internal registers (A and B) consisting of

13 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data holding

registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control

register (FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), a

user accessible scratchpad register (SPR), and an Alternate Function Register (AFR).

[1] The baud rate register and AFR register sets are accessible only when CS is a logic 0 and LCR[7] is a

Holding Register (RHR) has not been read following the loading of a character, or the

receive trigger interrupt is generated when RX FIFO level is equal to the program RX

trigger value.

The interrupts are enabled by IER[3:0]. Care must be taken when handling these

interrupts. Following a reset, if the transmitter interrupt is enabled, the SC16C2552B will

issue an interrupt to indicate that the Transmit Holding Register is empty. The ISR register

provides the current singular highest priority interrupt only. A condition can exist where a

higher priority interrupt may mask the lower priority interrupt(s). Only after servicing the

higher pending interrupt will the lower priority interrupt(s) be reflected in the status

SC16C2552B_3 © NXP B.V. 2009. All rights reserved.

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive

Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the

center of each stop bit received or each time the receive holding register (RHR) is read.

The actual time-out value is 4 character time.

The SC16C2552B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see

Table 5).

The generator divides the input 16× clock by any divisor from 1 to (2

16

− 1). The

SC16C2552B divides the basic external clock by 16. The basic 16× clock provides table

rates to support standard and custom applications using the same system design. The

rate table is configured via the DLL and DLM internal register functions. Customized baud

rates can be achieved by selecting the proper divisor values for the MSB and LSB

sections of baud rate generator.

SC16C2552B_3 © NXP B.V. 2009. All rights reserved.

The SC16C2552B FIFO trigger level provides additional flexibility to the user for block

mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an

empty location(s). The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA

mode is de-activated (DMA Mode 0), the SC16C2552B activates the interrupt output pin

for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1),

the user takes the advantage of block mode operation by loading or unloading the FIFO in

a block sequence determined by the receive trigger level and the transmit FIFO. In this

mode, the SC16C2552B sets the interrupt output pin when characters in the transmit

FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger

RI and CD inputs, respectively. MCR signals DTR (bit 0) and RTS (bit 1) are used to

control the modem DSR and CTS inputs, respectively. The transmitter output (TX) and the

receiver input (RX) are disconnected from their associated interface pins, and instead are

connected together internally (see Figure 4). The CTS, DSR, CD, and RI are

disconnected from their normal modem control inputs pins, and instead are connected

internally to RTS, DTR, OP2 and OP1. Loopback test data is entered into the transmit

holding register via the user data bus interface, D0 to D7. The transmit UART serializes

the data and passes the serial data to the receive UART via the internal loopback

connection. The receive UART converts the serial data back into parallel data that is then