FUNCTIONAL BLOCK DIAGRAM
REV. G
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a
Signal Conditioning ADC
AD7710
FEATURES
Charge Balancing ADC
24 Bits, No Missing Codes
0.0015% Nonlinearity
2-Channel Programmable Gain Front End
Gains from 1 to 128
Differential Inputs
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single- or Dual-Supply Operation
Low Power (25 mW Typ) with Power-Down Mode
(7 mW Typ)
APPLICATIONS
Weigh Scales
Thermocouples
Process Control
Smart Transmitters
Chromatography
GENERAL DESCRIPTION
The AD7710 is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a strain gage or transducer and outputs a serial
digital word. It employs a sigma-delta conversion technique to
realize up to 24 bits of no missing codes performance. The input
signal is applied to a proprietary programmable gain front end
based around an analog modulator. The modulator output is
processed by an on-chip digital filter. The first notch of this
digital filter can be programmed via the on-chip control register,
allowing adjustment of the filter cutoff and settling time.
The part features two differential analog inputs and a differen-
tial reference input. Typically, one of the channels will be used
as the main channel with the second channel used as an auxil-
iary input to measure a second voltage periodically. It can be
operated from a single supply (by tying the V
SS
pin to AGND),
provided that the input signals on the analog inputs are more
positive than –30 mV. By taking the V
SS
pin negative, the part
can convert signals down to –V
REF
on its inputs. The AD7710
thus performs all signal conditioning and conversion for a single-
or dual-channel system.
The AD7710 is ideal for use in smart, microcontroller based
systems. Input channel selection, gain settings, and signal polar-
ity can be configured in software using the bidirectional serial
port. The AD7710 contains self-calibration, system calibration,
and background calibration options, and also allows the user to
read and write the on-chip calibration registers.
CMOS construction ensures low power dissipation, and a soft-
ware programmable power-down mode reduces the standby
power consumption to only 7 mW typical. The part is available
in a 24-lead, 0.3 inch-wide, plastic and hermetic dual-in-line
package (DIP) as well as a 24-lead small outline (SOIC) package.
PRODUCT HIGHLIGHTS
1. The programmable gain front end allows the AD7710 to
accept input signals directly from a strain gage or transducer,
removing a considerable amount of signal conditioning.
2. The AD7710 is ideal for microcontroller or DSP processor
applications with an on-chip control register that allows
control over filter cutoff, input gain, channel selection, signal
polarity, and calibration modes.
3. The AD7710 allows the user to read and write the on-chip
calibration registers. This means that the microcontroller has
much greater control over the calibration procedure.
4. No missing codes ensures true, usable, 23-bit dynamic range
coupled with excellent ±0.0015% accuracy. The effects of
temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
CLOCK
GENERATION
SERIAL INTERFACE
CONTROL
REGISTER
OUTPUT
REGISTER
CHARGE-BALANCING A/D
CONVERTER
DIGITAL
FILTER
AD7710
M
U
X
PGA
AGND DGND MODE SDATA SCLK A0
MCLK
OUT
MCLK
IN
AIN1(+)
AIN1(–)
REF
IN (–)
REF
IN (+)
SYNC
4.5A
A = 1 – 128
DRDY
TFSRFS
REF OUT
2.5V REFERENCE
AV
DD
AV
DD
20A
AIN2(+)
AIN2(–)
I
OUT
V
SS
V
BIAS
AV
DD
DV
DD
AUTO-ZEROED
-
MODULATOR
AD7710* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
AN-202: An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change
AN-241: Evaluation Board for the AD7710 High Resolution
(24-Bits) Sigma-Delta A/D Converter
AN-283: Sigma-Delta ADCs and DACs
AN-311: How to Reliably Protect CMOS Circuits Against
Power Supply Overvoltaging
AN-388: Using Sigma-Delta Converters-Part 1
AN-389: Using Sigma-Delta Converters-Part 2
AN-397: Electrically Induced Damage to Standard Linear
Integrated Circuits:
AN-406: Using the AD771X Family of 24-Bit Sigma-Delta
A/D Converters
AN-553: Adjusting the Calibration Coefficients on the
AD771X Family of ADCs
AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma-
Delta ADC
AN-615: Peak-to-Peak Resolution Versus Effective
Resolution
Data Sheet
AD7710: Military Data Sheet
AD7710: Signal Conditioning ADC Data Sheet
TOOLS AND SIMULATIONS
Sigma-Delta ADC Tutorial
REFERENCE MATERIALS
Technical Articles
Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
MS-2210: Designing Power Supplies for High Speed ADC
Part 1: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
Part 2: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
DESIGN RESOURCES
AD7710 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD7710 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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REV. G–2–
Parameter A, S Versions
1
Unit Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches 60 Hz
22 Bits min For Filter Notch = 100 Hz
18 Bits min For Filter Notch = 250 Hz
15 Bits min For Filter Notch = 500 Hz
12 Bits min For Filter Notch = 1 kHz
Output Noise Tables I and II Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity @ +25°C ±0.0015 % of FSR max Filter Notches 60 Hz
T
MIN
to T
MAX
±0.003 % of FSR max Typically ±0.0003%
Positive Full-Scale Error
2,
3
See Note 4 Excluding Reference
Full-Scale Drift
5
1 µV/°C typ Excluding Reference. For Gains of 1, 2
0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Unipolar Offset Error
2
See Note 4
Unipolar Offset Drift
5
0.5 µV/°C typ For Gains of 1, 2
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2
See Note 4
Bipolar Zero Drift
5
0.5 µV/°C typ For Gains of 1, 2
0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128
Gain Drift 2 ppm/°C typ
Bipolar Negative Full-Scale Error
2
@ 25°C ±0.003 % of FSR max Excluding Reference
T
MIN
to T
MAX
±0.006 % of FSR max Typically ±0.0006%
Bipolar Negative Full-Scale Drift
5
1 µV/°C typ Excluding Reference. For Gains of 1, 2
0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR) 100 dB min At DC and AV
DD
= 5 V
90 dB min At DC and AV
DD
= 10 V
Common-Mode Voltage Range
6
V
SS
to AV
DD
V min to V max
Normal-Mode 50 Hz Rejection
7
100 dB min For Filter Notches of 10, 25, 50 Hz, ±0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection
7
100 dB min For Filter Notches of 10, 30, 60 Hz, ±0.02 × f
NOTCH
Common-Mode 50 Hz Rejection
7
150 dB min For Filter Notches of 10, 25, 50 Hz, ±0.02 × f
NOTCH
Common-Mode 60 Hz Rejection
7
150 dB min For Filter Notches of 10, 30, 60 Hz, ±0.02 × f
NOTCH
DC Input Leakage Current
7
@ 25°C10 pA max
T
MIN
to T
MAX
1 nA max
Sampling Capacitance
7
20 pF max
Analog Inputs
8
Input Voltage Range
9
For Normal Operation. Depends on Gain Selected
0 to +V
REF
10
nom Unipolar Input Range (B/U Bit of Control Register = 1)
±V
REF
nom Bipolar Input Range (B/U Bit of Control Register = 0)
Input Sampling Rate, f
S
See Table III
Reference Inputs
REF IN(+) – REF IN(–) Voltage
11
2.5 to 5 V min to V max For Specified Performance. Part Is Functional with
Lower V
REF
Voltages
Input Sampling Rate, f
S
f
CLK IN
/256
NOTES
1
Temperature ranges are as follows: A Version, –40°C to +85°C; S Version, –55°C to +125°C. See also Note 16.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
DD
+ 30 mV and V
SS
– 30 mV.
7
These numbers are guaranteed by design and/or characterization.
8
The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source
resistance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute
voltage on the analog inputs should not go more positive than AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
10
V
REF
= REF IN(+) – REF IN(–).
11
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
AD7710–SPECIFICATIONS
(AV
DD
= +5 V 5%; DV
DD
= +5 V 5%; V
SS
= 0 V or –5 V 5%; REF IN(+) = +2.5 V;
REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise noted. All specifications T
MIN
to T
MAX
, unless otherwise noted.)

AD7705BRUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3V/5V 1mW 2-Ch Diff 16-Bit
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