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AD7705BRUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
REV. G
–12–
AD7710
1k
10
0.1
10 1k 10k
100
1
100
NOTCH FREQUENCY – Hz
OUTPUT NOISE – ␮V
GAIN OF 16
GAIN OF 32
GAIN OF 64
GAIN OF 128
Figure 2b. Output Noise vs. Gain and Notch
Frequency (Gains of 16 to 128)
The basic connection diagram for the part is shown in Figure 3.
This figure shows the AD7710 in the external clocking mode
with both the AV
DD
and DV
DD
pins being driven from the ana-
log 5 V supply. Some applications have separate supplies for
both AV
DD
and DV
DD
, and in some cases, the analog supply
exceeds the 5 V digital supply (see the Power Supplies and
Grounding section).
REF IN(+)
REF OUT
AIN1(+)
AIN1(–)
AIN2(+)
AGND
DGND
MCLK IN
MCLK OUT
MODE
SCLK
SDATA
DRDY
TFS
RFS
REF IN(–)
V
BIAS
SYNC
A0
DIFFERENTIAL
ANALOG INPUT
ANALOG
GROUND
DIGITAL
GROUND
DATA
READY
TRANSMIT
(WRITE)
RECEIVE
(READ)
SERIAL
DATA
SERIAL
CLOCK
ADDRESS
INPUT
+5V
AD7710
10␮F
0.1␮F
0.1␮F
ANALOG
+5V SUPPLY
AV
DD
DV
DD
V
SS
I
OUT
AIN2(–)
DIFFERENTIAL
ANALOG INPUT
Figure 3. Basic Connection Diagram
Figure 2 show information similar to that outlined in Table I. In this plot, however, the output rms noise is shown for the full range
of available cutoffs frequencies. The numbers given in these plots are typical values at 25°C.
10k
100
0.1
10 1k 10k
1k
10
1
100
GAIN OF 1
GAIN OF 2
GAIN OF 4
GAIN OF 8
NOTCH FREQUENCY – Hz
OUTPUT NOISE – ␮V
Figure 2a. Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
CIRCUIT DESCRIPTION
The AD7710 is a sigma-delta A/D converter with on-chip digital
filtering for measuring wide dynamic range, low frequency sig-
nals in applications such as weigh scale, industrial control, or
process control. It contains a sigma-delta (or charge-balancing)
ADC, a calibration microcontroller with on-chip static RAM, a
clock oscillator, a digital filter, and a bidirectional serial commu-
nications port.
The part contains two programmable gain differential analog
input channels. The gain range is from 1 to 128 allowing the
part to accept unipolar signals of 0 mV to 20 mV and 0 V to
2.5 V, or bipolar signals in the range of ± 20 mV to ±2.5 V when
the reference input voltage equals 2.5 V. The input signal to the
selected analog input channel is continuously sampled at a rate
determined by the frequency of the master clock, MCLK IN,
and the selected gain (see Table III). A charge-balancing A/D
converter (sigma-delta modulator) converts the sampled signal
into a digital pulse train whose duty cycle contains the digital
information. The programmable gain function on the analog
input is also incorporated in this sigma-delta modulator with the
input sampling frequency being modified to give the higher
gains. A sinc
3
digital low-pass filter processes the output of the
sigma-delta modulator and updates the output register at a rate
determined by the first notch frequency of the filter. The output
data can be read from the serial port randomly or periodically at
any rate up to the output register update rate. The first notch of
this digital filter (and therefore its –3 dB frequency) can be
programmed via an on-chip control register. The programmable
range for this first notch frequency is 9.76 Hz to 1.028 kHz,
giving a programmable range for the –3 dB frequency of 2.58 Hz
to 269 Hz.
AD7710
REV. G
–13–
In operation, the analog signal sample is fed to the subtracter,
along with the output of the 1-bit DAC. The filtered difference
signal is fed to the comparator, which samples the difference
signal at a frequency many times that of the analog signal sam-
pling frequency (oversampling).
Oversampling is fundamental to the operation of sigma-delta
ADCs. Using the quantization noise formula for an ADC,
SNR = (6.02 × number of bits + 1.76) dB,
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
The AD7710 samples the input signal at a frequency of 39 kHz or
greater (see Table III). As a result, the quantization noise is
spread over a much wider frequency than that of the band of
interest. The noise in the band of interest is reduced still further
by analog filtering in the modulator loop, which shapes the
quantization noise spectrum to move most of the noise energy to
frequencies outside the bandwidth of interest. The noise perfor-
mance is thus improved from this 1-bit level to the performance
outlined in Tables I and II and in Figures 2a and 2b.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal. The digital data
that represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the compara-
tor. It can be retrieved as a parallel binary data-word using a
digital filter.
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first-order sigma-
delta ADC is shown in Figure 5. This contains only a first-order
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices, charge-balancing ADCs.
+FS
–FS
DAC
DIFFERENTIAL
AMPLIFIER
COMPARATOR
INTEGRATOR
V
IN
Figure 5. Basic Charge-Balancing ADC
The device consists of a differential amplifier (whose output is
the difference between the analog input and the output of a
1-bit DAC), an integrator and a comparator. The term charge
balancing comes from the fact that this system is a negative
feedback loop that tries to keep the net charge on the integrator
capacitor at zero, by balancing charge injected by the input
voltage with charge injected by the 1-bit DAC. When the analog
input is zero, the only contribution to the integrator output
comes from the 1-bit DAC. For the net charge on the integrator
capacitor to be zero, the DAC output must spend half its time at
+FS and half its time at –FS. Assuming ideal components, the
duty cycle of the comparator will be 50%.
When a positive analog input is applied, the output of the 1-bit
DAC must spend a larger proportion of the time at +FS, so the
duty cycle of the comparator increases. When a negative input
voltage is applied, the duty cycle decreases.
The AD7710 uses a second-order sigma-delta modulator and a
digital filter that provides a rolling average of the sampled out-
put. After power-up, or if there is a step change in the input
voltage, there is a settling time that must elapse before valid
data is obtained.
The AD7710 provides a number of calibration options that can
be programmed via the on-chip control register. A calibration
cycle may be initiated at any time by writing to this control
register. The part can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. Other system components may also be included in
the calibration loop to remove offset and gain errors in the input
channel, using the system calibration mode. Another option is a
background calibration mode where the part continuously per-
forms self-calibration and updates the calibration coefficients.
Once the part is in this mode, the user does not have to issue
periodic calibration commands to the device or to recalibrate
when there is a change in the ambient temperature or power
supply voltage.
The AD7710 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the device calibra-
tion coefficients and also to write its own calibration coefficients
to the part from prestored values in E
2
PROM. This gives the
microprocessor much greater control over the AD7710’s cali-
bration procedure. It also means that the user can verify that the
calibration is correct by comparing the coefficients after calibra-
tion with prestored values in E
2
PROM.
The AD7710 can be operated in single-supply systems if the analog
input voltage does not go more negative than –30 mV. For larger
bipolar signals, a V
SS
of –5 V is required by the part. For battery
operation, the AD7710 also offers a programmable standby
mode that reduces idle power consumption to typically 7 mW.
THEORY OF OPERATION
The general block diagram of a sigma-delta ADC is shown in
Figure 4. It contains the following elements:
• A sample-hold amplifier.
• A differential amplifier or subtracter.
• An analog low-pass filter.
• A 1-bit A/D converter (comparator).
• A 1-bit DAC.
• A digital low-pass filter.
S/H AMP
COMPARATOR
DIGITAL DATA
DIGITAL
FILTER
ANALOG
LOW-PASS
FILTER
DAC
Figure 4. General Sigma-Delta ADC
REV. G
–14–
AD7710
Input Sample Rate
The modulator sample frequency for the device remains at
f
CLK IN
/512 (19.5 kHz @ f
CLK IN
= 10 MHz) regardless of the
selected gain. However, gains greater than ×1 are achieved by a
combination of multiple input samples per modulator cycle and
scaling the ratio of reference capacitor to input capacitor. As a
result of the multiple sampling, the input sample rate of the device
varies with the selected gain (see Table III). The effective input
impedance is 1/C × f
S
where C is the input sampling capacitance
and f
S
is the input sample rate.
Table III. Input Sampling Frequency vs. Gain
Gain Input Sampling Frequency (f
S
)
1f
CLK IN
/256 (39 kHz @ f
CLK IN
= 10 MHz)
22 × f
CLK IN
/256 (78 kHz @ f
CLK IN
= 10 MHz)
44 × f
CLK IN
/256 (156 kHz @ f
CLK IN
= 10 MHz)
88 × f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
16 8 × f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
32 8 × f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
64 8 × f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
128 8 × f
CLK IN
/256 (312 kHz @ f
CLK IN
= 10 MHz)
DIGITAL FILTERING
The AD7710 digital filter behaves like a similar analog filter,
with a few minor differences.
First, because digital filtering occurs after the A-to-D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise super-
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this, and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7710 has over-
range headroom built into the sigma-delta modulator and digital
filter, which allows overrange excursions of 5% above the analog
input range. If noise signals are larger than this, consideration
should be given to analog input filtering, or to reducing the
input channel voltage so that its full scale is half that of the
analog input channel full scale. This will provide an overrange
capability greater than 100% at the expense of reducing the
dynamic range by 1 bit (50%).
Filter Characteristics
The cutoff frequency of the digital filter is determined by the
value loaded to bits FS0 to FS11 in the control register. At the
maximum clock frequency of 10 MHz, the minimum cutoff
frequency of the filter is 2.58 Hz while the maximum program-
mable cutoff frequency is 269 Hz.
Figure 6 shows the filter frequency response for a cutoff fre-
quency of 2.62 Hz, which corresponds to a first filter notch
frequency of 10 Hz. This is a (sinx/x)
3
response (also called
sinc
3
) that provides >100 dB of 50 Hz and 60 Hz rejection.
Programming a different cutoff frequency via FS0–FS11 does
not alter the profile of the filter response, but changes the fre-
quency of the notches as outlined in the Control Register section.
GAIN – dB
FREQUENCY – Hz
0
–240
07010 20 30 40 50 60
–40
–80
–120
–160
–200
–20
–60
–100
–140
–180
–220
Figure 6. Frequency Response of AD7710 Filter
Since the AD7710 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs, and
data from the output will be invalid after a step change until the
settling time has elapsed. The settling time depends upon the
notch frequency chosen for the filter. The output data rate
equates to this filter notch frequency and the settling time of the
filter to a full-scale step input that is four times the output data
period. In applications using both input channels, the settling
time of the filter must be allowed to elapse before data from the
second channel is accessed.
Post Filtering
The on-chip modulator provides samples at a 19.5 kHz output
rate. The on-chip digital filter decimates these samples to pro-
vide data at an output rate that corresponds to the programmed
first notch frequency of the filter. Because the output data rate
exceeds the Nyquist criterion, the output rate for a given band-
width will satisfy most application requirements. However,
there may be some applications that require a higher data rate
for a given bandwidth and noise performance. Applications that
need a higher data rate will require some post filtering following
the digital filter of the AD7710.
For example, if the required bandwidth is 7.86 Hz but the
required update rate is 100 Hz, the data can be taken from the
AD7710 at the 100 Hz rate, giving a –3 dB bandwidth of 26.2 Hz.
Post filtering can be applied to this to reduce the bandwidth and
output noise to the 7.86 Hz bandwidth level, while maintaining
an output rate of 100 Hz.
Post filtering can also to reduce the output noise from the device
for bandwidths below 2.62 Hz. At a gain of 128, the output rms
noise is 250 nV. This is essentially device noise or white noise, and
because the input is chopped, the noise has a flat frequency
response. By reducing the bandwidth below 2.62 Hz, the noise in
the resultant pass band can be reduced. A reduction in bandwidth
by a factor of 2 results in a √2 reduction in the output rms noise.
This additional filtering will result in a longer settling time.
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AD7705BRUZ-REEL7

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Buy AD7705BRUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3V/5V 1mW 2-Ch Diff 16-Bit
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