AD7710
REV. G
–27–
CLOCK
GENERATION
SERIAL INTERFACE
CONTROL
REGISTER
OUTPUT
REGISTER
CHARGE-BALANCING A/D
CONVERTER
DIGITAL
FILTER
AD7710
M
U
X
PGA
AGND DGND MODE SDATA SCLK A0
MCLK
OUT
MCLK
I
AIN1(+)
AIN1(–)
REF
IN(–)
REF
IN(+)
SYNC
A = 1 – 128
DRDY
TFSRFS
AIN2(+)
AIN2(–)
V
SS
V
BIAS
AV
DD
DV
DD
2.5V
REFERENCE
REF
OUT
ANALOG
5V SUPPLY
R
R
ACTIVE
GAGE
DUMMY
GAGE
N
AUTO-ZEROED
Σ-∆
MODULATOR
Figure 19. Strain-Gage Application with the AD7710
CLOCK
GENERATION
SERIAL INTERFACE
CONTROL
REGISTER
OUTPUT
REGISTER
CHARGE-BALANCING A/D
CONVERTER
AUTO-ZEROED
Σ-∆
MODULATOR
DIGITAL
FILTER
AD7710
M
U
X
PGA
AGND DGND MODE SDATA SCLK A0
MCLK
OUT
MCLK
IN
AIN1(+)
AIN1(–)
SYNC
A = 1 – 128
DRDY
TFSRFS
AIN2(+)
AIN2(–)
V
SS
V
BIAS
AV
DD
DV
DD
2.5V
REFERENCE
R
R
ACTIVE
GAGE
DUMMY
GAGE
DIGITAL
5V SUPPLY
ANALOG SUPPLY
EXCITATION
CURRENT
REF IN(+)
R =
V
REF
I
EXCITATION
REF IN(–)
REF
OUT
Figure 20. Alternate Scheme for Generating AD7710 Reference Voltage
APPLICATIONS
Figure 19 shows a strain gage interfaced directly to one of the
analog input channels of the AD7710. The differential inputs to
the AD7710 are connected directly to the bridge network of the
strain gage. In the diagram shown, the on-chip reference of the
AD7710 provides the voltage for the bridge network and also
provides the reference voltage for the AD7710. An alternative
scheme, outlined in Figure 20, shows the analog positive supply
voltage powering the bridge network and the AD7710, with the
reference voltage for the AD7710 generated across a resistor
that is placed in series with the bridge network. In this case, the
value of the reference resistor is determined by the required
reference voltage divided by the value of the excitation current.
The on-chip PGA allows the AD7710 to handle an analog input
voltage range as low as 20 mV full scale. The differential inputs
of the part allow this analog input range to have an absolute
value anywhere between V
SS
and AV
DD
.
