AD7705BRUZ-REEL7 Datasheet AD7705BRUZ-REEL7, AD7710ARZ, AD7710ANZ | P22-P24

AD7710

REV. G

–21–

Read Operation

As with self-clocking mode, data can be read from either the

output register, the control register, or the calibration registers.

A0 determines whether the data read accesses data from the

control register or from the output/calibration registers. This A0

signal must remain valid for the duration of the serial read

operation. With A0 high, data is accessed from either the output

accessed from the control register.

The function of the DRDY line is dependent only on the output

update rate of the device and the reading of the output data

the output data register. It is reset high when the last bit of data

(either 16th bit or 24th bit) is read from the output register. If

data is not read from the output register, the DRDY line will

remain low. The output register will continue to be updated at

the output update rate, but DRDY will not indicate this. A read

from the device in this circumstance will access the most recent

word in the output register. If a new data-word becomes avail-

able to the output register while data is being read from the

output register, DRDY will not indicate this and the new data-

word will be lost to the user. DRDY is not affected by reading

from the control register or the calibration register.

Data can be accessed from the output data register only when

DRDY is low. If RFS goes low while DRDY is high, no data

transfer will take place. DRDY does not have any effect on reading

data from the control register or from the calibration registers.

Write Operation

Data can be written to either the control register or calibration

registers. In either case, the write operation is not affected by

the DRDY line and does not have any effect on the status of

DRDY. A write operation to the control registers or calibration

Figure 11 shows a write operation to the AD7710. A0 determines

whether a write operation transfers data to the control register or to

the calibration registers. This A0 signal must remain valid for the

duration of the serial write operation. The falling edge of TFS

enables the internally generated SCLK output. The serial data

to be loaded to the AD7710 must be valid on the rising edge of

this SCLK signal. Data is clocked into the AD7710 on the rising

edge of the SCLK signal with the MSB transferred first. On the

last active high time of SCLK, the LSB is loaded to the AD7710.

Subsequent to the next falling edge of SCLK, the SCLK output is

turned off. (The timing diagram in Figure 11 assumes a pull-up

resistor on the SCLK line.)

External Clocking Mode

The AD7710 is configured for external clocking mode by

tying the MODE pin low. In this mode, SCLK of the AD7710

is configured as an input, and an external serial clock must be

provided to this SCLK pin. This external clocking mode is

designed for direct interface to systems that provide a serial

clock output that is synchronized to the serial data output,

including microcontrollers such as the 80C51, 87C51, 68HC11,

68HC05, and most digital signal processors.

SDATA (I)

SCLK (O)

TFS (I)

A0 (I)

MSB LSB

Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation

REV. G

–22–

AD7710

Figures 12a and 12b show timing diagrams for reading from the

AD7710 in external clocking mode. In Figure 12a, all the data is

read from the AD7710 in one read operation. In Figure 12b, the

data is read from the AD7710 over a number of read operations.

Both read operations show a read from the AD7710’s output

data register. A read from the control register or calibration

registers is similar, but, in these cases, the DRDY line is not

related to the read function. Depending on the output update

rate, it can go low at any stage in the control/calibration register

read cycle without affecting the read, and its status should be

ignored. A read operation from either the control or calibration

registers must always read 24 bits of data.

Figure 12a shows a read operation from the AD7710 where

RFS remains low for the duration of the data-word transmis-

sion. With DRDY low, the RFS input is brought low. The input

SCLK signal should be low between read and write operations.

RFS going low places the MSB of the word to be read on the

serial data line. All subsequent data bits are clocked out on a

high to low transition of the serial clock and are valid prior to

the following rising edge of this clock. The penultimate falling

edge of SCLK clocks out the LSB and the final falling edge

resets the DRDY line high. This rising edge of DRDY turns off

the serial data output.

Figure 12b shows a timing diagram for a read operation where

RFS returns high during the transmission of the word and

returns low again to access the rest of the data-word. Timing

parameters and functions are very similar to that outlined for

Figure 12a, but Figure 12b has a number of additional times to

show timing relationships when RFS returns high in the middle

of transferring a word.

RFS should return high during a low time of SCLK. On the

rising edge of RFS, the SDATA output is turned off. DRDY

remains low and will remain low until all bits of the data-word

are read from the AD7710, regardless of the number of times

RFS changes state during the read operation. Depending on the

time between the falling edge of SCLK and the rising edge of

RFS, the next bit (BIT N+1) may appear on the data bus before

RFS goes high. When RFS returns low again, it activates the

SDATA output. When the entire word is transmitted, the

DRDY line will go high, turning off the SDATA output as

shown in Figure 12a.

RFS (I)

SCLK (I)

SDATA (O)

LSB

MSB

THREE-STATE

A0 (I)

DRDY (O)

Figure 12a. External Clocking Mode, Output Data Read Operation

THREE-STATE

MSB

BIT N

BIT N+1

SDATA (O)

SCLK (I)

RFS (I)

A0 (I)

DRDY (O)

Figure 12b. External Clocking Mode, Output Data Read Operation (

RFS

Returns High during Read Operation)

AD7710

REV. G

–23–

Write Operation

Data can be written to either the control register or calibration

registers. In either case, the write operation is not affected by

the DRDY line and does not have any effect on the status of

DRDY. A write operation to the control register or the calibra-

tion register must always write 24 bits.

Figure 13a shows a write operation to the AD7710 with TFS

remaining low for the duration of the operation. A0 determines

whether a write operation transfers data to the control register

or to the calibration registers. This A0 signal must remain valid

for the duration of the serial write operation. As before, the

serial clock line should be low between read and write opera-

tions. The serial data to be loaded to the AD7710 must be valid

on the high level of the externally applied SCLK signal. Data is

clocked into the AD7710 on the high level of this SCLK signal

with the MSB transferred first. On the last active high time of

SCLK, the LSB is loaded to the AD7710.

Figure 13b shows a timing diagram for a write operation to the

AD7710 with TFS returning high during the operation and

returning low again to write the rest of the data-word. Timing

parameters and functions are very similar to those outlined for

Figure 13a, but Figure 13b has a number of additional times to

show timing relationships when TFS returns high in the middle

of transferring a word.

Data to be loaded to the AD7710 must be valid prior to the

rising edge of the SCLK signal. TFS should return high during

the low time of SCLK. After TFS returns low again, the next bit

of the data-word to be loaded to the AD7710 is clocked in on

next high level of the SCLK input. On the last active high time

of the SCLK input, the LSB is loaded to the AD7710.

SCLK (I)

SDATA (I)

A0 (I)

MSB

LSB

TFS (I)

Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation

SCLK (I)

SDATA (I)

TFS (I)

A0 (I)

MSB

BIT N BIT N+1

Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation

(

TFS

Returns High during Write Operation)

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AD7705BRUZ-REEL7

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3V/5V 1mW 2-Ch Diff 16-Bit

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AD7705BRUZ-REEL7

AD7705BRUZ-REEL7

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