L6566A Application information
Doc ID 13794 Rev 4 19/52
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5 V)
Figure 8. Zero current detection block, triggering block, oscillator block and
related logic
Vcc
(pin 5)
GD
(pin 4)
Vcc_OK
Vcc
ON
Vcc
OFF
Vcc
restart
I
charge
0.85 mA
Short circuit occurs here
t
t
t
t
T
rep
< 0.03T
rep
100 mV
50 mV
DRIV ER
+
-
5.7V
ZCD
PWM
GD
R
S
Q
BLANKING
TIME
COMP
+Vin
Q
L6566A
5V
-
+
MONO
STABLE
R
Z1
blanking
START
R
Z2
CS
VFF
TURN-ON
LOGIC
4:1
Counter
Strobe
FAULT
S/H
Reset
line
FFWD
OSCILLATOR
OSC
R
T
915
7
4
13
11
Rs
Application information L6566A
20/52 Doc ID 13794 Rev 4
5.2 Zero current detection and triggering block; oscillator block
The zero current detection (ZCD) and triggering blocks switch on the external MOSFET if a
negative-going edge falling below 50 mV is applied to the input (pin 11, ZCD). To do so the
triggering block must be previously armed by a positive-going edge exceeding 100 mV.
This feature is typically used to detect transformer demagnetization for QR operation, where
the signal for the ZCD input is obtained from the transformer’s auxiliary winding used also to
supply the L6566A. The triggering block is blanked for T
BLANK
= 2.5 µs after MOSFET turn-
off to prevent any negative-going edge that follows leakage inductance demagnetization
from triggering the ZCD circuit erroneously.
The voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the
internal diagram of the ZCD block of
Figure 8. The upper clamp is typically located at 5.7 V,
while the lower clamp is located at -0.4 V. The interface between the pin and the auxiliary
winding is a resistor divider. Its resistance ratio is properly chosen (see
Section 5.11) and
the individual resistance values (R
Z1
, R
Z2
) are such that the current sourced and sunk by
the pin be within the rated capability of the internal clamps (± 3 mA).
At converter power-up, when no signal is coming from the ZCD pin, the oscillator starts up
the system. The oscillator is programmed externally by means of a resistor (R
T
) connected
from pin OSC (13) to ground. With good approximation the oscillation frequency f
osc
is:
Equation 2
(with f
osc
in kHz and R
T
in kW). As the device is turned on, the oscillator starts immediately;
at the end of the first oscillator cycle, the voltage on the ZCD pin being zero, the MOSFET is
turned on, therefore starting the first switching cycle right at the beginning of the second
oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the
current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the
transformer starts demagnetization. If this completes (so a negative-going edge appears on
the ZCD pin) after a time exceeding one oscillation period T
osc
=1/f
osc
from the previous turn-
on, the MOSFET is turned on again - with some delay to ensure minimum voltage at turn-on
– and the oscillator ramp is reset. If, instead, the negative-going edge appears before T
osc
has elapsed, it is ignored and only the first negative-going edge after T
osc
turns on the
MOSFET and synchronizes the oscillator. In this way one or more drain ringing cycles are
skipped (“valley-skipping mode”,
Figure 9) and the switching frequency is prevented from
exceeding f
osc
.
T
3
osc
R
102
f
Figure 9. Drain ringing cycle skipping as the load is gradually reduced
Pin = Pin'
(limit condition)
P
in
= P
in''
< P
in'
P
in
= P
in'''
< P
in''
t
V
DS
T
FW
T
osc
T
V
T
ON
t
V
DS
T
osc
t
V
DS
T
osc
L6566A Application information
Doc ID 13794 Rev 4 21/52
Note: When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Therefore one or more longer switching
cycles is compensated by one or more shorter cycles, and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.
If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is
smaller than the arming threshold for some reason (e.g. a heavy damping of drain
oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used),
MOSFET turn-on cannot be triggered. This case is identical to what happens at startup: at
the end of the next oscillator cycle the MOSFET is turned on, and a new switching cycle
takes place after skipping no more than one oscillator cycle.
The operation described so far does not consider the blanking time T
BLANK
after MOSFET
turn-off, and actually T
BLANK
does not come into play as long as the following condition is
met:
Equation 3
where D is the MOSFET duty cycle. If this condition is not met, nothing changes
substantially: the time during which MOSFET turn-on is inhibited is extended beyond T
osc
by
a fraction of T
BLANK
. As a consequence, the maximum switching frequency is a little lower
than the programmed value f
osc
and valley-skipping mode may take place slightly earlier
than expected. However this is quite unusual: setting f
osc
= 150 kHz, the phenomenon can
be observed at duty cycles higher than 60%. See
Section 5.11 for further implications of
T
BLANK
.
If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an
internal pull-up keeps the ZCD pin close to 2 V during MOSFET OFF-time to prevent noise
from false triggering the detection block. When this pull-up is active, the ZCD pin may not be
able to go below the triggering threshold, which would stop the converter. To allow auto-
restart operation, while ensuring minimum operating frequency in these conditions, the
oscillator frequency that retriggers MOSFET turn-on is that of the external oscillator divided
by 128. Additionally, to prevent malfunction at converter startup, the pull-up is disabled
during the initial soft-start (see
Section 5.10). However, to ensure a correct startup, at the
end of the soft-start phase, the output voltage of the converter must meet the condition:
Equation 4
where Ns is the turn number of the secondary winding, Naux the turn number of the
auxiliary winding, and I
ZCD
the maximum pull-up current (130 μA).
osc
BLANK
T
T
1D
ZCD1Z
IR
Naux
Ns
Vout >

L6566A

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Power Factor Correction - PFC Multi Mode PWM Controller
Lifecycle:
New from this manufacturer.
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