L6566A Datasheet L6566ATR, L6566A | P37-P39

L6566A Application information

Doc ID 13794 Rev 4 37/52

5.12 Brownout protection

Brownout protection is basically a not-latched device shutdown function activated when a

condition of mains undervoltage is detected. There are several reasons why it may be

desirable to shut down a converter during a brownout condition, which occurs when the

mains voltage falls below the minimum specification of normal operation.

Firstly, a brownout condition may cause overheating of the PFC front-end due to an excess

of RMS current. Secondly, brownout can also cause the PFC pre-regulator to work open

loop. This could be dangerous to the PFC itself and the downstream converter, should the

input voltage return abruptly to its rated value, given the slow response of PFC to transient

events. Finally, spurious restarts may occur during converter power-down, therefore causing

the output voltage not to decay to zero monotonically.

The L6566A shutdown upon brownout is accomplished by means of an internal comparator,

as shown in the block diagram of

Figure 25, which shows the basic circuit usage. The

inverting input of the comparator, available on the AC_OK pin (16), is supposed to sense a

voltage proportional to either the RMS or the peak mains voltage; the non-inverting input is

internally referenced to 0.485 V with 35 mV hysteresis. If the voltage applied on the AC_OK

pin before the device starts operating does not exceed 0.485 V or if it falls below 0.45 V

while the device is running, The AC_OK signal goes high, the Vcc_PFC pin is open and the

device shuts down, with the soft-start capacitor discharged and the gate-drive output low.

Additionally, in case the device has been latched off by some protection function (in which

case Vcc is oscillating between V

ccON

and V

ccON

- 0.5 V), the AC_OK voltage falling below

0.45 V clears the latch. This feature can be used to allow a quicker restart as the input

source is removed.

Figure 25. Brownout protection: internal block diagram and timing diagram

L6566A

AC_ FAIL

AC_OK

Vcc

0.485V

0.45V

15 µA

Sensed

voltage

Vcc

(pin 5)

(pin 4)

Vout

VAC_OK

(pin 16)

0.45V

HYS

15 µA

Vcc_PFC

(pin 6)

AC _FAIL

Sensed voltage

Vsen

OFF

0.485V

Application information L6566A

38/52 Doc ID 13794 Rev 4

While the brownout protection is active the startup generator keeps on working but, there

being no PWM activity, the Vcc voltage continuously oscillates between the startup and the

HV generator restart thresholds, as shown in the timing diagram of

Figure 25.

The brownout comparator is provided with current hysteresis in addition to voltage

hysteresis: an internal 15 µA current sink is ON as long as the voltage applied on the

AC_OK pin is such that the AC_FAIL signal is high. This approach provides an additional

degree of freedom: it is possible to set the ON threshold and the OFF threshold separately

by properly choosing the resistors of the external divider (see

Equation 13 and 14 below).

With just voltage hysteresis, instead, fixing one threshold automatically fixes the other one

depending on the built-in hysteresis of the comparator.

With reference to

Figure 25, the following relationships can be established for the ON

(Vsen

) and OFF (Vsen

OFF

) thresholds of the sensed voltage:

Equation 13

which, solved for R

and R

, yield:

Equation 14

It is usually convenient to not use additional dividers connected to high-voltage rails

because this could make it difficult to meet no-load consumption targets envisaged by

energy-saving regulations.

Figure 26 shows a simple voltage sensing technique that makes

use of the divider already used by the PFC control chip to sense the AC mains voltage with

just the addition of an extra tap.

The small-signal NPN Q and the capacitor C

create a peak detector, so that the information

of the RMS mains voltage can be found across C

. The tap position determines the DC

voltage to be sensed by the AC_OK pin. It is convenient to use a level as high as possible to

minimize the effect of V

changes with temperature. However, it may be necessary to limit

the maximum sensed voltage below 7 V to prevent Q’s emitter reverse breakdown; it would

not be destructive because the reverse current would be quite small (the resistors seen by

Figure 26. AC voltage sensing with the L6566A

OFF

45.0

45.0Vsen

485.0

1015

485.0Vsen

−

+⋅=

−

45.0Vsen

45.0

RR;

1015

Vsen078.1Vsen

OFF

OFFON

−

⋅

⋅−

−

L6566A

Rectified

input voltage

Sensed

voltage:

Vsen < 7V

MULT

L6561

L6562/A

L6563

Vcc

AC_OK

For minimum

temperature drift

L6566A Application information

Doc ID 13794 Rev 4 39/52

the base terminal are several ten kW) but this could distort the signal on the MULT pin of the

PFC chip and adversely affect the operation of the pre-regulator. C

needs to be quite a big

capacitor (in the μF) to have small residual ripple superimposed on the DC level; as a rule-

of-thumb, use a time constant (R

+ R

)·C

at least 4-5 times the maximum line cycle

period, then fine-tune if needed, considering also transient conditions such as mains

missing cycles.

If temperature effects are critical, the NPN Q can be replaced by a PNP-NPN pair arranged

as shown in

Figure 26 on the right-hand side; other sensing techniques may also be

adopted.

The voltage on the pin is clamped upwards at about 3.15 V; then, if the function is not used,

the pin must be connected to Vcc through a resistor (220 to 680 kΩ).

5.13 Slope compensation

The MODE/SC pin (12), when not connected to VREF, provides a voltage ramp during

MOSFET ON-time synchronous to that of the internal oscillator sawtooth, with 0.8 mA

minimum current capability. This ramp is intended for implementing additive slope

compensation on current sense. This is needed to avoid the sub-harmonic oscillation that

arises in all peak-current-mode-controlled converters working at fixed frequency in

continuous conduction mode with a duty cycle close to or exceeding 50%.

Figure 27. Slope compensation waveforms

The compensation is realized by connecting a programming resistor between this pin and

the current sense input (pin 7, CS). The CS pin must be connected to the sense resistor with

another resistor to make a summing node on the pin. Since no ramp is delivered during

MOSFET OFF-time (see

Figure 27), no external component other than the programming

resistor is needed to ensure a clean operation at light loads.

Note: The addition of the slope compensation ramp reduces the available dynamics of the current

signal; therefore, the value of the sense resistor must be determined taking this into

account. Note also that the burst-mode threshold (in terms of power) changes slightly.

If slope compensation is not required with FF operation, the pin is left floating.

Internal

oscillator

(pin 4)

MODE/ SC

(pin 12)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P52

L6566A

Mfr. #:

Buy L6566A

Manufacturer:

STMicroelectronics

Description:

Power Factor Correction - PFC Multi Mode PWM Controller

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

L6566A

L6566A

Products related to this Datasheet