L6566A Application information
Doc ID 13794 Rev 4 31/52
Figure 19. Possible interfaces between the L6566A and a PFC controller
To prevent intermittent operation of the PFC stage, some hysteresis is provided: if the
internal switch is open, it is closed (which re-enables the PFC pre-regulator) when V
COMP
exceeds V
COMPL
> V
COMPO
. Additionally, to reject V
COMP
undershoots during transients,
V
COMP
must stay below V
COMPO
for more than 1024 oscillator cycles in order for the
Vcc_PFC pin to open. Entering burst-mode (V
COMP
< V
COMPBM
) opens Vcc_PFC
immediately.
Besides pin 6 going open, when V
COMP
falls below V
COMPO
the UVLO threshold is set 2.4 V
below to compensate for the drop of the voltage delivered by the self-supply circuit that
occurs at light load (see
Section 5.4).
5.9 Latched disable function
The device is equipped with a comparator having the non-inverting input externally available
at the DIS pin (8) and with the inverting input internally referenced to 4.5 V. As the voltage
on the pin exceeds the internal threshold, the device is immediately shut down and its
consumption reduced to a low value.
The information is latched and it is necessary to let the voltage on the Vcc pin go below the
UVLO threshold to reset the latch and restart the device. To keep the latch supplied as long
as the converter is connected to the input source, the HV generator is activated periodically
so that Vcc oscillates between the startup threshold V
ccON
and V
ccON
- 0.5 V. Activating the
HV generator in this way cuts its power dissipation approximately by three (as compared to
the case of continuous conduction) and keeps peak silicon temperature close to the average
value.
To let the L6566A restart it is then necessary to disconnect the converter from the input
source. Pulling pin 16 (AC_OK) below the disable threshold (see
Section 5.12) stops the HV
generator until Vcc falls below Vcc
restart
, so that the latch can be cleared and a quicker
restart is allowed as the input source is removed. This operation is shown in the timing
diagram of
Figure 20.
This function is useful to easily implement a latched overtemperature protection by biasing
the pin with a divider from VREF, where the upper resistor is an NTC physically located
close to a heating element like the MOSFET, or the transformer. The DIS pin is a high-
impedance input, it is therefore prone to pick-up noise, which might give origin to undesired
latch-off of the device. It is possible to bypass the pin to ground with a small film capacitor
(e.g. 1-10 nF) to prevent any malfunctioning of this kind.
L6566A
Vcc_PFC6
5
Vcc
Vcc
L6566A
Vcc_PFC6
L6563
5
Vcc
RUN
4.7kΩ
22 k
Ω
10
L6561
L6562
L6563
