AT91R40807-33AU Datasheet AT91R40807-33AU, AT91R40807-33AI, AT91R40807-33AC | P10-P12

AT91R40807

1345DS–ATARM–02/02

extended SRAM. Then, the NRST must be reasserted by external circuitry after the level

on the pin BMS is changed.

The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like

any standard PIO line.

Remap Command The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,

Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to

allow these vectors to be redefined dynamically by the software, the AT91R40807

Microcontrollers use a remap command that enables switching between the boot mem-

ory and the internal primary SRAM bank addresses. The remap command is accessible

through the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control

devices (connected to chip-selects 1 to 7) is required. The remap operation can only be

changed back by an internal reset or an NRST assertion.

Abort Control The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI

is asserted when accessing an undefined address in the EBI address space.

No abort is generated when reading the internal memory or by accessing the internal

peripherals, whether the address is defined or not.

External Bus Interface The External Bus Interface handles the accesses between addresses 0x0040 0000 and

0xFFC0 0000. It generates the signals that control access to the external devices, and

can be configured from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports

byte-, half-word- and word- aligned accesses.

For each of these banks, the user can program:

• Number of wait states

• Number of data float times (wait time after the access is finished to prevent any bus

contention in case the device is too long in releasing the bus)

• Data bus-width (8-bit or 16-bit).

• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit

device (Byte Access Select mode) or two 8-bit devices in parallel that emulate a 16-

bit memory (Byte Write Access mode).

The External Bus Interface features also the Early Read Protocol, configurable for all the

devices, that significantly reduces access time requirements on an external device in

the case of single-clock cycle access.

Table 3. Boot Mode Select

BMS Boot Memory

1 Internal 32-bit extended SRAM

0 External 16-bit memory on NCS0

AT91R40807

1345DS–ATARM–02/02

Peripherals The AT91R40807 peripherals are connected to the 32-bit wide Advanced Peripheral

Bus. Peripheral registers are only word accessible

– byte and half-word accesses are

not supported. If a byte or a half-word access is attempted, the memory controller auto-

matically masks the lowest address bits and generates an word access.

Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte

address space).

Peripheral Registers The following registers are common to all peripherals:

• Control Register

– write only register that triggers a command when a one is written

to the corresponding position at the appropriate address. Writing a zero has no

effect.

• Mode Register

– read/write register that defines the configuration of the peripheral.

Usually has a value of 0x0 after a reset.

• Data Registers

– read and/or write register that enables the exchange of data

between the processor and the peripheral.

• Status Register

– read only register that returns the status of the peripheral.

• Enable/Disable/Status Registers

– shadow command registers. Writing a one in the

Enable Register sets the corresponding bit in the Status Register. Writing a one in

the Disable Register resets the corresponding bit and the result can be read in the

Status Register. Writing a bit to zero has no effect. This register access method

maximizes the efficiency of bit manipulation, and enables modification of a register

with a single non-interruptible instruction, replacing the costly read-modify-write

operation.

Unused bits in the peripheral registers are shown as “

–” and must be written at 0 for

upward compatibility. These bits read 0.

Peripheral Interrupt Control The Interrupt Control of each peripheral is controlled from the status register using the

interrupt mask. The status register bits are ANDed to their corresponding interrupt mask

bits and the result is then ORed to generate the Interrupt Source signal to the Advanced

Interrupt Controller.

The interrupt mask is read in the Interrupt Mask Register and is modified with the Inter-

rupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or

mask) makes it possible to enable or disable peripheral interrupt sources with a non-

interruptible single instruction. This eliminates the need for interrupt masking at the AIC

or core level in real-time and multi-tasking systems.

Peripheral Data Controller The AT91R40807 microcontroller has a 4-channel PDC dedicated to the two on-chip

USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of

each USART.

The user interface of a PDC channel is integrated in the memory space of each USART.

It contains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer

Counter Register (RCR or TCR). When the programmed number of transfers are per-

formed, a status bit indicating the end of transfer is set in the USART Status Register

and an interrupt can be generated.

AT91R40807

1345DS–ATARM–02/02

System Peripherals

PS: Power-saving The Power-saving feature optimizes power consumption, enabling the software to stop

the ARM7TDMI clock (idle mode), restarting it when the module receives an interrupt (or

reset). It also enables on-chip peripheral clocks to be enabled and disabled individually,

matching power consumption and application need.

AIC: Advanced Interrupt

Controller

The Advanced Interrupt Controller has an 8-level priority, individually maskable, vec-

tored interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from:

• The external fast interrupt line (FIQ)

• The three external interrupt request lines (IRQ0-IRQ2)

• The interrupt signals from the on-chip peripherals.

The AIC is largely programmable offering maximum flexibility, and its vectoring features

reduce the real-time overhead in handling interrupts.

The AIC also features a spurious vector, which reduces spurious interrupt handling to a

minimum, and a protect mode that facilitates the debug capabilities.

PIO: Parallel I/O Controller The AT91R40807 microcontroller has 32 programmable I/O lines. Six pins are dedi-

cated as general-purpose I/O pins. Other I/O lines are multiplexed with an external

signal of a peripheral to optimize the use of available package pins. The PIO controller

enables generation of an interrupt on input change and insertion of a simple input glitch

filter on any of the PIO pins.

WD: Watchdog The Watchdog is built around a 16-bit counter and is used to prevent system lock-up if

the software becomes trapped in a deadlock. It can generate an internal reset or inter-

rupt, or assert an active level on the dedicated pin NWDOVF. All programming registers

are password-protected to prevent unintentional programming.

SF: Special Function The AT91R40807 microcontroller provide registers that implement the following special

functions.

• Chip identification

• RESET status

• Protect mode

• Write protection for the AT91R40807 internal 128-Kbyte memory

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

AT91R40807-33AU

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ARM Microcontrollers - MCU LQFP IND TEMP

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