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AT91R40807
1345DS–ATARM–02/02
JTAG/ICE Debug ARM Standard Embedded In-circuit Emulation is supported via the JTAG/ICE port. The
pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con-
nected to a host computer via the external ICE interface.
In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identi-
fies the microcontroller. This is not fully IEEE1149.1 compliant.
Memory Controller The ARM7TDMI processor address space is 4G bytes. The memory controller decodes
the internal 32-bit address bus and defines three address spaces:
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices (memory or peripherals) controlled
by the EBI
• Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.
Internal Memories The AT91R40807 microcontroller integrates 8K bytes of primary internal SRAM. All
internal memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-
word (16-bit) or word (32-bit) accesses are supported and are executed within one
cycle. Fetching Thumb or ARM instructions is supported and internal memory can store
twice as many Thumb instructions as ARM ones.
The primary SRAM bank is mapped at address 0x0 (after the remap command), allow-
ing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the
software. The rest of the bank can be used for stack allocation (to speed up context sav-
ing and restoring) or as data and program storage for critical algorithms.
The AT91R40807 also integrates an extended memory bank of 128K bytes at address
0x0010 0000. Placing the SRAM on-chip and using the 32-bit data bus bandwidth maxi-
mizes the microcontroller performance and minimizes the system power consumption.
The 32-bit bus increases the effectiveness of the use of the ARM instruction set, and the
ability of processing data that is wider than 16-bit, thus making optimal use of the
ARM7TDMI advanced performance.
Being able to dynamically update application software in the 128-Kbyte SRAM adds an
extra dimension to the AT91R40807. This 128-Kbyte SRAM can also be used to vali-
date the code to be stored in the on-chip ROM memory prior to mass production of the
AT91M40807. At system boot, the code is downloaded from external nonvolatile mem-
ory to this on-chip extended SRAM. In order to prevent accidental write to the extended
SRAM during the ROM emulation, a write detection feature has been implemented.
The AT91R40807 microcontroller ROM version (AT91M40807) integrates 128K bytes of
internal ROM at address 0x0010 0000. The ROM version offers a reduced-cost option
for high-volume applications in which the software is stable.
Boot Mode Select The ARM reset vector is at address 0x0. After the NRST line is released, the
ARM7TDMI executes the instruction stored at this address. This means that this
address must be mapped in nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of
the NRST selects the type of boot memory. The Boot Mode depends on BMS (see
Table 3).
The AT91R40807 supports boot in on-chip extended SRAM, for the purpose of emulat-
ing ROM versions. In this case, the microcontroller must first boot from external
nonvolatile memory, and ensure that a valid program is downloaded in the on-chip
