5
AT91R40807
1345DS–ATARM–02/02
Architectural
Overview
The AT91R40807 microcontroller integrates an ARM7TDMI with Embedded ICE inter-
face, memories and peripherals. The architecture consists of two main buses, the
Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for
maximum performance and controlled by the memory controller, the ASB interfaces the
ARM7TDMI processor with the on-chip 32-bit memories, the External Bus Interface
(EBI) and the AMBA
™
Bridge. The AMBA Bridge drives the APB, which is designed for
accesses to on-chip peripherals and optimized for low power consumption.
The AT91R40807 microcontroller implements the ICE port of the ARM7TDMI processor
on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for tar-
get debugging.
Memories The AT91R40807 microcontroller embeds 136K bytes of internal SRAM. The internal
memory is directly connected to the 32-bit data bus and is single-cycle accessible. This
provides maximum performance of 36 MIPS at 40 MHz by using the ARM instruction set
of the processor, minimizing system power consumption and improving on the perfor-
mance of separate memory solutions.
The AT91R40807 microcontroller features an External Bus Interface (EBI), which
enables connection of external memories and application-specific peripherals. The EBI
supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit
device. The EBI implements the early read protocol, enabling faster memory accesses
than standard memory interfaces.
Peripherals The AT91R40807 microcontroller integrates several peripherals, which are classified as
system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA
Bridge, and can be programmed with a minimum number of instructions. The peripheral
register set is composed of control, mode, data, status and enable/disable/status
registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip
USARTs and on- and off-chip memories address space without processor intervention.
Most importantly, the PDC removes the processor interrupt handling overhead, making
it possible to transfer up to 64K contiguous bytes without reprogramming the start
address, thus increasing the performance of the microcontroller, and reducing the power
consumption.
System Peripherals The External Bus Interface (EBI) controls the external memory or peripheral devices via
an 8- or 16-bit data bus and is programmed through the APB. Each chip select line has
its own programming register.
The Power-saving (PS) module implements the Idle mode (ARM7TDMI core clock
stopped until the next interrupt) and enables the user to adapt the power consumption of
the microcontroller to application requirements (independent peripheral clock control).
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the
internal peripherals and the four external interrupt lines (including the FIQ), to provide an
interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority
controller and, using the Auto-vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user
to select specific pins for on-chip peripheral input/output functions, and general-purpose
input/output signal pins. The PIO controller can be programmed to detect an interrupt on
a signal change from each line.
