SC16C850IBS,128 Datasheet SC16C850IBS,128, SC16C850IBS,151, SC16C850IBS/Q900,5 | P34-P36

Product data sheet Rev. 2 — 11 November 2010 34 of 55

NXP Semiconductors

SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.17 Flow Control Trigger Level High (FLWCNTH)

This 8-bit register is used to store the receive FIFO high threshold levels to start/stop

transmission during hardware/software flow control. Table 27

shows the FLWCNTH

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.18 Flow Control Trigger Level Low (FLWCNTL)

This 8-bit register is used to store the receive FIFO low threshold levels to start/stop

transmission during hardware/software flow control. Table 28

shows the FLWCNTL

[1] For 32-byte FIFO mode, refer to Section 7.3.

7.19 Clock Prescaler (CLKPRES)

This register hold values for the clock prescaler.

Table 27. FLWCNTH register bits description

Bit Symbol Description

7:0 FLWCNTH[7:0] This register stores the programmable HIGH threshold level for

hardware and software flow control for 128-byte FIFO mode

[1]

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

Table 28. FLWCNTL register bits description

Bit Symbol Description

7:0 FLWCNTL[7:0] This register stores the programmable LOW threshold level for

hardware and software flow control for 128-byte FIFO mode

[1]

0x00 = trigger level is set to 1

0x01 = trigger level is set to 1

...

0x80 = trigger level is set to 128

Table 29. Clock Prescaler register bits description

Bit Symbol Description

7:4 CLKPRES[7:4] reserved

3:0 CLKPRES[3:0] Clock Prescaler value. Reset to 0.

Product data sheet Rev. 2 — 11 November 2010 35 of 55

NXP Semiconductors

SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.20 RS-485 Turn-around time delay (RS485TIME)

The value in this register controls the turn-around time of the external line transceiver in

bit time. In automatic 9-bit mode RTS

or DTR pin is used to control the direction of the line

driver, after the last bit of data has been shifted out of the transmit shift register the UART

will count down the value in this register. When the count value reaches zero, the UART

will assert RTS

or DTR pin (logic 0) to turn the external RS-485 transceiver around for

receiving.

7.21 Advanced Feature Control Register 2 (AFCR2)

Table 30. RS-485 programmable turn-around time register bits description

Bit Symbol Description

7:0 RS485TIME[7:0] External RS-485 transceiver turn-around time delay. The value

represents the bit time at the programmed baud rate.

Table 31. Advanced Feature Control Register 2 register bits description

Bit Symbol Description

7:6 AFCR2[7:6] reserved

5 AFCR2[5] RTSInvert. Invert RTS or DTR signal in automatic 9-bit mode.

logic 0 = RTS or DTR is set to 0 by the UART during transmission,

and to 1 during reception

logic 1 = RTS or DTR is set to 1 by the UART during transmission,

and to 0 during reception

4 AFCR2[4] RTSCon. Enable the transmitter to control RTS

or DTR pin in

automatic 9-bit mode.

logic 0 = transmitter does not control RTS or DTR pin

logic 1 = transmitter controls RTS

or DTR pin

3 AFCR2[3] RS485 RTS/DTR. Select RTS

or DTR pin to control the external

transceiver.

logic 0 = RTS pin is used to control the external transceiver

logic 1 = DTR pin is used to control the external transceiver

2 AFCR2[2] TXDisable. Disable transmitter

logic 0 = transmitter is enabled

logic 1 = transmitter is disabled

1 AFCR2[1] RXDisable. Disable receiver

logic 0 = receiver is enabled

logic 1 = receiver is disabled

0 AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode

logic 0 = normal RS-232 mode

logic 1 = enable 9-bit mode

Product data sheet Rev. 2 — 11 November 2010 36 of 55

NXP Semiconductors

SC16C850

2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder

7.22 Advanced Feature Control Register 1 (AFCR1)

[1] It takes 4 XTAL1 clocks to reset the device.

Table 32. Advanced Feature Control Register 1 register bits description

Bit Symbol Description

7:5 AFCR1[7:5] reserved

4 AFCR1[4] Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.

logic 0 = RX input is level-sensitive. If RX pin is LOW, the UART will

not go to sleep. Once the UART is in Sleep mode, it will wake up if RX

pin goes LOW.

logic 1 = RX input is edge-sensitive. UART will go to sleep even if RX

pin is LOW, and will wake up when RX pin toggles.

3 AFCR1[3] reserved

2 AFCR1[2] RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to

DTR/DSR.

logic 0 = RTS and CTS signals are used for hardware flow control.

logic 1 = DTR and DSR signals are used for hardware flow control.

RTS and CTS retain their functionality.

1 AFCR1[1] SReset. Software Reset. A write to this bit will reset the UART. Once the

UART is reset this bit is automatically set to 0.

[1]

0 AFCR1[0] TSR Interrupt. Select TSR interrupt mode

logic 0 = transmit empty interrupt occurs when transmit FIFO falls

below the trigger level or becomes empty.

logic 1 = transmit empty interrupt occurs when transmit FIFO falls

below the trigger level, or becomes empty and the last stop bit has

been shifted out of the Transmit Shift Register.

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SC16C850IBS,128

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NXP Semiconductors

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IC UART SGL W/FIFO 32HVQFN

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SC16C850IBS,128

SC16C850IBS,128

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