SC16C850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 11 November 2010 40 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency =
[3] 1 kΩ pull-up resistor on IRQ
pin.
[4] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Table 38. Dynamic characteristics - Motorola or 68 mode
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
DD
±
10 %; unless otherwise specified.
Symbol Parameter Conditions V
DD
=2.5V V
DD
=3.3V Unit
Min Max Min Max
t
WH
pulse width HIGH 6 - 6 - ns
t
WL
pulse width LOW 6 - 6 - ns
t
w(clk)
clock pulse width 12.5 - 12.5 - ns
f
XTAL1
frequency on pin XTAL1
[1][2]
-80-80MHz
t
su(A)
address set-up time 10 - 10 - ns
t
h(A)
address hold time 15 - 15 - ns
t
su(RWL-CSL)
set-up time from R/W LOW to CS LOW 10 - 10 - ns
t
su(RWH-CSL)
set-up time from R/W HIGH to CS LOW 10 - 10 - ns
t
w(CS)
CS pulse width 25 pF load 50 - 20 - ns
t
d(CS)
CS delay time 25 pF load 20 - 10 - ns
t
d(CS-Q)
delay time from CS to data output 25 pF load - 50 - 20 ns
t
dis(CS-QZ)
disable time from CS to
high-impedance data output
25 pF load - 20 - 20 ns
t
h(CS-RWH)
hold time from CS to R/W HIGH 10 - 10 - ns
t
d(RW)
R/W delay time 10 - 10 - ns
t
su(D-CSH)
set-up time from data input to CS HIGH 15 - 15 - ns
t
h(CSH-D)
data input hold time after CS HIGH 15 - 15 - ns
t
d(modem-IRQL)
delay time from modem to IRQ LOW
[3]
- 40 - 30 ns
t
d(CS-IRQH)R
read delay time from CS to IRQ HIGH
[3]
- 40 - 30 ns
t
d(stop-IRQL)
delay time from stop to IRQ LOW
[4]
-1T
RCLK
-1T
RCLK
s
t
d(CS-TX)W
write delay time from CS to TX
[4]
8T
RCLK
24T
RCLK
8T
RCLK
24T
RCLK
s
t
d(start-IRQL)
delay time from start to IRQ LOW
[3][4]
-1T
RCLK
-1T
RCLK
s
t
d(CS-IRQH)W
write delay time from CS to IRQ HIGH
[3]
- 55 - 45 ns
t
d(CS-Q)W
write delay time from CS to data output - 40 - 33 ns
t
w(RESET_N)
pulse width on pin RESET 10 - 10 - ns
N baud rate divisor 1 (2
16
− 1) 1 (2
16
− 1)
1
t
wclk()
---------------
