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SC16C850IBS,128

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
SC16C850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 11 November 2010 37 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.23 SC16C850 external reset condition and software reset
These two reset methods are identical and will reset the internal registers as indicated in
Table 33
.
Table 33. Reset state for registers
Register Reset state
IER IER[7:0] = 0
FCR FCR[7:0] = 0
ISR ISR[7:1] = 0; ISR[0] = 1
LCR LCR[7:0] = 0
MCR MCR[7:0] = 0
LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR MSR[7:4] = input signals; MSR[3:0] = 0
EFCR EFCR[7:0] = 0
SPR SPR[7:0] = 1
DLL undefined
DLM undefined
TXLVLCNT TXLVLCNT[7:0] = 0
RXLVLCNT RXLVLCNT[7:0] = 0
EFR EFR[7:0] = 0
Xon1 undefined
Xon2 undefined
Xoff1 undefined
Xoff2 undefined
TXINTLVL TXINTLVL[7:0] = 0
RXINTLVL RXINTLVL[7:0] = 0
FLWCNTH FLWCNTH[7:0] = 0
FLWCNTL FLWCNTL[7:0] = 0
CLKPRES CLKPRES[7:0] = 0
RS485TIME RS485TIME[7:0] = 0
AFCR2 AFCR2[7:0] = 0
AFCR1 AFCR1[7:0] = 0
Table 34. Reset state for outputs
Output Reset state
TX logic 1
RTS
logic 1
DTR
logic 1
INT logic 0
IRQ
open-drain
SC16C850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 11 November 2010 38 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
8. Limiting values
9. Static characteristics
[1] Hysteresis input.
[2] Except XTAL2; XTAL2 V
OL
is 1 V typical.
[3] Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.
[4] Activated by LOWPWR pin.
Table 35. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage - 7 V
V
n
voltage on any other pin V
SS
− 0.3 V
DD
+0.3 V
T
amb
ambient temperature operating in free air −40 +85 °C
T
stg
storage temperature −65 +150 °C
P
tot
/pack total power dissipation per
package
- 500 mW
Table 36. Static characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
DD
±
10 %; unless otherwise specified.
Symbol Parameter Conditions V
DD
=2.5V V
DD
=3.3V Unit
Min Max Min Max
V
IL(clk)
clock LOW-level input voltage XTAL1 pin −0.3 0.45 −0.3 0.6 V
V
IH(clk)
clock HIGH-level input voltage XTAL1 pin 1.8 V
DD
2.4 V
DD
V
V
IL
LOW-level input voltage except XTAL1 clock,
LOWPWR pin
−0.3 0.65 −0.3 0.8 V
LOWPWR pin
[1]
−0.3 0.65 −0.3 0.8 V
V
IH
HIGH-level input voltage except XTAL1 clock,
LOWPWR pin
1.6-2.0-V
LOWPWR pin
[1]
1.6 V
DD
2.2 V
DD
V
V
OL
LOW-level output voltage I
OL
=4mA
[2]
---0.4V
I
OL
=2mA
[2]
-0.4- -V
V
OH
HIGH-level output voltage I
OH
= −4mA
[2]
--2.2-V
I
OH
= −800 μA
[2]
1.85 - - - V
I
LIL
LOW-level input leakage current - 10 - 10 μA
I
LIH
HIGH-level input leakage current - 10 - 10 μA
I
L(clk)
clock leakage current LOW-level - 30 - 30 μA
HIGH-level - 30 - 30 μA
I
DD
supply current f = 5 MHz - 3 - 3 mA
I
DD(sleep)
sleep mode supply current
[3]
-50-50μA
I
DD(lp)
low-power mode supply current
[4]
-50-50μA
C
i
input capacitance - 5 - 5 pF
SC16C850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 11 November 2010 39 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
10. Dynamic characteristics
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency =
[3] 10 % of the data bus output voltage level.
[4] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Table 37. Dynamic characteristics - Intel or 16 mode
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
DD
±
10 %; unless otherwise specified.
Symbol Parameter Conditions V
DD
=2.5V V
DD
=3.3V Unit
Min Max Min Max
t
WH
pulse width HIGH 6 - 6 - ns
t
WL
pulse width LOW 6 - 6 - ns
t
w(clk)
clock pulse width 12.5 - 12.5 - ns
f
XTAL1
frequency on pin XTAL1
[1][2]
-80-80MHz
t
su(A)
address set-up time 10 - 5 - ns
t
h(A)
address hold time 10 - 5 - ns
t
d(CS-IOR)
delay time from CS to IOR 10 - 5 - ns
t
w(IOR)
IOR pulse width time 35 - 26 - ns
t
h(IOR-CS)
hold time from IOR to chip select 0 - 0 - ns
t
d(IOR)
IOR delay time 10 - 10 - ns
t
d(IOR-Q)
delay time from IOR to data output 25 pF load - 35 - 26 ns
t
dis(IOR-QZ)
disable time from IOR to
high-impedance data output
[3]
25 pF load - 17 - 15 ns
t
d(CSL-IOWL)
delay time from CS LOW to
IOW LOW
10 - 5 - ns
t
w(IOW)
IOW pulse width time 15 - 20 - ns
t
h(IOW-CS)
hold time from IOW to CS 0-0-ns
t
d(IOW)
IOW delay time 15 - 20 - ns
t
su(D-IOWH)
set-up time from data input to
IOW
HIGH
10 - 5 - ns
t
h(IOWH-D)
data input hold time after IOW HIGH 10 - 5 - ns
t
d(IOW-Q)
delay time from IOW to data output 25 pF load - 40 - 33 ns
t
d(modem-INT)
delay time from modem to INT 25 pF load - 35 - 24 ns
t
d(IOR-INTL)
delay time from IOR to INT LOW 25 pF load - 35 - 24 ns
t
d(stop-INT)
delay time from stop to INT 25 pF load
[4]
-1T
RCLK
-1T
RCLK
s
t
d(start-INT)
delay time from start to INT 25 pF load
[4]
-1T
RCLK
-1T
RCLK
s
t
d(IOW-TX)
delay time from IOW to TX 25 pF load
[4]
8T
RCLK
24T
RCLK
8T
RCLK
24T
RCLK
s
t
d(IOW-INTL)
delay time from IOW to INT LOW 25 pF load - 55 - 45 ns
t
w(RESET)
pulse width on pin RESET 10 - 10 - ns
N baud rate divisor 1 (2
16
− 1) 1 (2
16
− 1)
1
t
wclk()
---------------
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SC16C850IBS,128

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Buy SC16C850IBS,128
Manufacturer:
NXP Semiconductors
Description:
IC UART SGL W/FIFO 32HVQFN
Lifecycle:
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