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SC16C850IBS,128
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
P49-P51
P52-P54
P55-P55
SC16C850
All informatio
n provided in this d
ocument is subje
ct to legal disclai
mers.
© NXP B.V
. 2010. All rights r
eserved.
Product data sheet
Rev
. 2 — 11 November 2010
43 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/dec
oder
Fig 15.
Modem input/output timin
g (16 mode)
t
d(IOW
-Q)
change of state
t
d(modem-INT)
t
d(IOR-INTL)
002aac409
change of state
change of state
change of state
active
active
active
activ
e
active
active
active
change of state
RTS
DTR
IOW
CD
CTS
DSR
INT
IOR
RI
t
d(modem-INT)
t
d(modem-INT)
(1)
CS
timing during a write cycle. See
Figure 1
1
.
(2)
CS
timing during a read cycle. See
Figure 13
.
Fig 16.
Modem input/output timin
g (68 mode)
t
d(CS-Q)W
change of state
t
d(modem-IRQL)
t
d(modem-IRQL)
t
d(CS-IRQH)R
002aac63
2
t
d(modem-IRQL)
change of state
change of state
change of state
active
active
active
activ
e
active
active
active
change of state
RTS
DTR
CS (write)
(1)
CD
CTS
DSR
IRQ
CS (read)
(2)
RI
SC16C850
All informatio
n provided in this d
ocument is subje
ct to legal disclai
mers.
© NXP B.V
. 2010. All rights r
eserved.
Product data sheet
Rev
. 2 — 11 November 2010
44 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/dec
oder
(1)
INT is active when RX FIFO fills up to tr
igger level or a time
-out condition happens (see
Section 6.8
).
(2)
INT is cleared when RX FIFO
drops below trigger level.
Fig 17.
Re
ceive timing in 16 mode
D0
D1
D2
D3
D4
D5
D6
D7
active
active
16 baud rate clock
002aac41
0
RX
INT
(1)(2)
IOR
t
d(IOR-INTL)
t
d(stop-INT)
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
star
t
bit
data bits (0 to 7)
next data
star
t
bit
(1)
IRQ
is active when RX FIFO fills up
to tr
igger level or time-
out condition happens (see
Section 6.8
).
(2)
IRQ
is cleared when RX FIFO drops below trigger leve
l.
Fig 18.
Re
ceive timing in 68 mode
D0
D1
D2
D3
D4
D5
D6
D7
active
active
16 baud rate clock
002aac63
3
t
d(CS-IRQH)R
next data
star
t
bit
stop
bit
parity
bit
star
t
bit
t
d(stop-IRQL)
RX
IRQ
(1)(2)
CS (read)
data bits (0 to 7)
5 data bits
6 data bits
7 data bits
SC16C850
All informatio
n provided in this d
ocument is subje
ct to legal disclai
mers.
© NXP B.V
. 2010. All rights r
eserved.
Product data sheet
Rev
. 2 — 11 November 2010
45 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/dec
oder
(1)
INT is active when TX FI
FO is empty or TX FIF
O drops below trigger level.
(2)
INT is cleared when ISR is read or T
X FIFO fills up to trigger level.
Fig 19.
T
ransmit
timing in 16 mode
active
transmitter ready
active
16 baud rate clock
002aac41
3
t
d(IOW
-INTL)
INT
(1)(2)
IOW
active
D0
D1
D2
D3
D4
D5
D6
D7
TX
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
star
t
bit
data bits (0 to 7)
next data
star
t
bit
t
d(start-INT)
t
d(IOW
-TX)
(1)
IRQ
is active when TX FIFO is emp
ty or
TX FIFO drops below trigger level.
(2)
IRQ
is cleared when ISR is read or TX
FIFO fills up to
trigger level.
Fig 20.
T
ransmit
timing in 68 mode
D0
D1
D2
D3
D4
D5
D6
D7
active
TX ready
active
16 baud rate clock
002aac63
4
t
d(CS-IRQH)W
star
t
bit
t
d(start-IRQL)
TX
IRQ
(1)(2)
CS (write)
data bits (0 to 7)
active
t
d(CS-TX)W
5 data bits
6 data bits
7 data bits
parity
bit
stop
bit
next data
star
t
bit
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P42
P43-P45
P46-P48
P49-P51
P52-P54
P55-P55
SC16C850IBS,128
Mfr. #:
Buy SC16C850IBS,128
Manufacturer:
NXP Semiconductors
Description:
IC UART SGL W/FIFO 32HVQFN
Lifecycle:
New from this manufacturer.
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