LTC1871-7
19
18717fd
applicaTions inForMaTion
During this inductor charging interval, the output capacitor
must supply the load current and a significant droop in
the output voltage can occur. Generally, it is a good idea
to choose a value of inductor I
L
between 25% and 40%
of I
IN(MAX)
. The alternative is to either increase the value
of the output capacitor or disable Burst Mode operation
using the MODE/SYNC pin.
Burst Mode operation can be defeated by connecting the
MODE/SYNC pin to a high logic-level voltage (either with
a control input or by connecting this pin to INTV
CC
). In
this mode, the burst clamp is removed, and the chip can
operate at constant frequency from continuous conduction
mode (CCM) at full load, down into deep discontinuous
conduction mode (DCM) at light load. Prior to skipping
pulses at very light load (i.e., <5% of full load), the control-
ler will operate with a minimum switch on-time in DCM.
Pulse skipping prevents a loss of control of the output at
very light loads and reduces output voltage ripple.
Efficiency Considerations
The efficiency of a switching regulator is equal to the out-
put power divided by the input power (¥100%). Percent
efficiency can be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + …),
where L1, L2, etc. are the individual loss components as a
percentage of the input power. It is often useful to analyze
individual losses to determine what is limiting the efficiency
and which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for the majority
of the losses in LTC1871-7 application circuits:
1. The supply current into V
IN
. The V
IN
current is the sum
of the DC supply current I
Q
(given in the Electrical Char-
acteristics) and the MOSFET driver and control currents.
The DC supply current into the V
IN
pin is typically about
650µA and represents a small power loss (much less
than 1%) that increases with V
IN
. The driver current
results from switching the gate capacitance of the power
MOSFET; this current is typically much larger than the
DC current. Each time the MOSFET is switched on and
then off, a packet of gate charge Q
G
is transferred from
INTV
CC
to ground. The resulting dQ/dt is a current that
must be supplied to the INTV
CC
capacitor through the
V
IN
pin by an external supply. If the IC is operating in
CCM:
I
Q(TOT)
≈ I
Q
= f • Q
G
P
IC
= V
IN
• (I
Q
+ f • Q
G
)
2. Power MOSFET switching and conduction losses:
P
FET
=
I
O(MAX)
1 D
MAX
2
R
DS(ON)
D
MAX
ρ
T
+ k V
O
2
I
O(MAX)
1 D
MAX
C
RSS
f
3. The I
2
R losses in the sense resistor can be calculated
almost by inspection.
P
R(SENSE)
=
I
O(MAX)
1 D
MAX
2
R
SENSE
D
MAX
4. The losses in the inductor are simply the DC input cur-
rent squared times the winding resistance. Expressing
this loss as a function of the output current yields:
P
R(WINDING)
=
I
O(MAX)
1 D
MAX
2
R
W
5. Losses in the boost diode. The power dissipation in the
boost diode is:
P
DIODE
= I
O(MAX)
• V
D
The boost diode can be a major source of power loss
in a boost converter. For 13.2V input, 42V output at
1.5A example given in Figure 9, a Schottky diode with
a 0.4V forward voltage would dissipate 600mW, which
represents about 1% of the input power. Diode losses
can become significant at low output voltages where
the forward voltage is a significant percentage of the
output voltage.
6. Other losses, including C
IN
and C
O
ESR dissipation and
inductor core losses, generally account for less than
2% of the total losses.
LTC1871-7
20
18717fd
applicaTions inForMaTion
Checking Transient Response
The regulator loop response can be verified by looking at
the load transient response at minimum and maximum
V
IN
. Switching regulators generally take several cycles to
respond to an instantaneous step in resistive load current.
When the load step occurs, V
O
immediately shifts by an
amount equal to (I
LOAD
)(ESR), and then C
O
begins to
charge or discharge (depending on the direction of the load
step) as shown in Figure 14. The regulator feedback loop
acts on the resulting error amp output signal to return V
O
to its steady-state value. During this recovery time, V
O
can
be monitored for overshoot or ringing that would indicate
a stability problem.
A second, more severe transient can occur when con-
necting loads with large (>1µF) supply bypass capacitors.
The discharged bypass capacitors are effectively put in
parallel with C
O
, causing a nearly instantaneous drop in
V
O
. No regulator can deliver enough current to prevent
this problem if the load switch resistance is low and it is
driven quickly. The only solution is to limit the rise time
of the switch drive in order to limit the inrush current di/
dt to the load.
Boost Converter Design Example
The design example given here will be for the circuit shown
in Figure 9. The input voltage is 8V to 28V, and the output
is 42V at a maximum load current of 1.5A.
1. The maximum duty cycle is:
D =
V
O
+ V
D
V
IN
V
O
+ V
D
=
42 + 0.4 8
42 + 0.4
= 81.1%
2. Pulse-skip operation is chosen so the MODE/SYNC pin
is shorted to INTV
CC
.
3. The operating frequency is chosen to be 250kHz to
reduce the size of the inductor. From Figure 5, the
resistor from the FREQ pin to ground is 100k.
4. An inductor ripple current of 40% of the maximum load
current is chosen, so the peak input current (which is
also the minimum saturation current) is:
I
IN(PEAK)
= 1+
χ
2
I
O(MAX)
1 D
MAX
= 1.2
1.5
1 0.81
= 9.47A
The inductor ripple current is:
I
L
= χ
I
O(MAX)
1 D
MAX
= 0.4
1.5
1 0.81
= 3.2A
And so the inductor value is:
L =
V
IN(MIN)
I
L
f
D
MAX
=
8
3.2 250k
0.81= 8.1µH
Figure 14a. Load Transient Response for the Circuit in Figure 9
Figure 14b. Load Transient Response for the Circuit in Figure 9
V
OUT
500mV/DIV
I
OUT
0.5A/DIV
0.5A
250µs/DIV
18717 F14a
1.5A
V
IN
= 8V
V
OUT
500mV/DIV
I
OUT
0.5A/DIV
0.5A
250µs/DIV
18717 F14b
1.5A
V
IN
= 28V
LTC1871-7
21
18717fd
applicaTions inForMaTion
The component chosen is a 6.8µH inductor made by
Cooper (part number DR127-6R8) which has a satura-
tion current of greater than 13.3A.
5. Because the duty cycle is 81%, the maximum SENSE
pin threshold voltage is reduced from its low duty cycle
typical value of 150mV to approximately 115mV. In ad-
dition, we need to apply a worst-case derating factor
to this SENSE threshold to account for manufacturing
tolerances within the IC. Finally, the nominal current
limit value should exceed the maximum load current
by some safety margin (in this case 50%). Therefore,
the value of the sense resistor is:
R
SENSE
= 0.8 V
SENSE(MAX)
1 D
MAX
1+
0.4
2
1.5 I
O(MAX)
= 0.8 0.115
1 0.81
1.2 1.5 1.5
= 6.5m
A 1W, 5mΩ resistor is used in this design.
6. The MOSFET chosen is a Vishay/Siliconix Si7370DP,
which has a BV
DSS
of greater than 60V and an R
DS(ON)
of less than 13mΩ at a V
GS
of 6V.
7. The diode for this design must handle a maximum DC
output current of 1.5A and be rated for a minimum
reverse voltage of V
OUT
, or 42V. A 3A, 60V diode from
Diodes Inc. (B360B) is chosen.
8. The output capacitor usually consists of a high valued
bulk C connected in parallel with a lower valued, low
ESR ceramic. Based on a maximum output ripple voltage
of 1%, or 50mV, the bulk C needs to be greater than:
C
OUT
I
OUT(MAX)
0.01 V
OUT
f
=
1.5
0.01 42 250k
= 14µF
The RMS ripple current rating for this capacitor needs
to exceed:
I
RMS(COUT)
I
O(MAX)
V
O
V
IN(MIN)
V
IN(MIN)
=
1.5
42 8
8
= 3.09A
T
o satisfy the low ESR, high frequency decoupling
requirements, two 10µF, 50V, X5R ceramic capacitors
are used (TDK part number C5750X5R1H106M). In
parallel with these, two 68µF, 100V electrolytic ca-
pacitors are used (Sanyo part number 100CV68FS).
Check the output ripple with a single oscilloscope
probe connected directly across the output capacitor
terminals, where the HF switching currents flow.
9.
The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and
the amount of input ripple the converter will safely
tolerate. For this particular design and lab setup a
560µF, 50V Sanyo electrolytic (50MV560AXL), in
parallel with two 10µF, 100V TDK ceramic capacitors
(C5750X5R1H106M) is required (the input and return
lead lengths are kept to a few inches, but the peak input
current is close to 10A!). As with the output node,
check the input ripple with a single oscilloscope probe
connected across the input capacitor terminals.
Figure 15. Switching Waveforms for the Converter
in Figure 9 at Minimum V
IN
(8V)
V
OUT
1V/DIV
I
L
2A/DIV
MOSFET
DRAIN
VOLTAGE
20V/DIV
1µs/DIV
18717 F15
V
IN
= 8V
I
OUT
= 0.5A
V
OUT
= 42V
D = 81%

LTC1871EMS-7#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Controllers No Rsense DC/DC Controller Boost, Flyback & SEPIC
Lifecycle:
New from this manufacturer.
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