LTC1871-7
22
18717fd
applicaTions inForMaTion
PC Board Layout Checklist
1. In order to minimize switching noise and improve
output load regulation, the GND pin of the LTC1871-7
should be connected directly to 1) the negative terminal
of the INTV
CC
decoupling capacitor, 2) the negative
terminal of the output decoupling capacitors, 3) the
bottom terminal of the sense resistor, 4) the negative
terminal of the input capacitor and 5) at least one via
to the ground plane immediately adjacent to Pin 6. The
ground trace on the top layer of the PC board should
be as wide and short as possible to minimize series
resistance and inductance.
2. Beware of ground loops in multiple layer PC boards.
Try to maintain one central ground node on the board
and use the input capacitor to avoid excess input ripple
for high output current power supplies. If the ground
plane is to be used for high DC currents, choose a path
away from the small-signal components.
3. Place the C
VCC
capacitor immediately adjacent to the
INTV
CC
and GND pins on the IC package. This capacitor
carries high di/dt MOSFET gate drive currents. A low
ESR and ESL 4.7µF ceramic capacitor works well here.
4. The high di/dt loop from the bottom terminal of the
output capacitor, through the power MOSFET, through
the boost diode and back through the output capacitors
should be kept as tight as possible to reduce inductive
ringing. Excess inductance can cause increased stress
on the power MOSFET and increase HF noise on the
output. If low ESR ceramic capacitors are used on the
output to reduce output noise, place these capacitors
close to the boost diode in order to keep the series
inductance to a minimum.
5. Check the stress on the power MOSFET by measuring
its drain-to-source voltage directly across the device
terminals (reference the ground of a single scope probe
directly to the source pad on the PC board). Beware
of inductive ringing which can exceed the maximum
specified voltage rating of the MOSFET. If this ringing
cannot be avoided and exceeds the maximum rating
of the device, either choose a higher voltage device
or specify an avalanche-rated power MOSFET. Not all
MOSFETs are created equal (some are more equal than
others).
6. Place the small-signal components away from high
frequency switching nodes. In the layout shown in
Figure 18, all of the small-signal components have
been placed on one side of the IC and all of the power
components have been placed on the other. This also
allows the use of a pseudo-Kelvin connection for the
signal ground, where high di/dt gate driver currents
flow out of the IC ground pin in one direction (to the
bottom plate of the INTV
CC
decoupling capacitor) and
small-signal currents flow in the other direction.
Figure 16. Switching Waveforms for the
Converter in Figure 9 at Maximum V
IN
(28V)
Figure 17. Efficiency vs Load Current and Input Voltage
for the Converter in Figure 9
V
OUT
1V/DIV
I
L
1A/DIV
MOSFET
DRAIN
VOLTAGE
20V/DIV
1µs/DIV
18717 F16
V
IN
= 28V
I
OUT
= 0.5A
V
OUT
= 42V
D = 27%
I
LOAD
(mA)
80
EFFICIENCY (%)
85
90
95
100
0.001 0.1 1 10
18717 F17
75
0.01
V
IN
= 8V
V
IN
= 12V
V
IN
= 28V
