18
COMMERCIAL TEMPERATURE RANGE
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
JTAG SUPPORT
The IDT72V71643 JTAG interface conforms to the Boundary-Scan stan-
dard IEEE-1149.1. This standard specifies a design-for-testability technique
called Boundary-Scan test (BST). The operation of the boundary-scan
circuitry is controlled by an external test access port (TAP) Controller.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT72V71643. It consists of three input pins and one output pin.
•Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with
any on-chip clock and thus remain independent. The TCK permits shifting of
test data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.
•Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to V
CC when it is not
driven from an external source.
•Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register
or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
•Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the
contents of either the instruction register or data register are serially shifted out
towards the TDO. The data out of the TDO is clocked on the falling edge of the
TCK pulses. When no data is shifted through the boundary scan cells, the TDO
driver is set to a high-impedance state.
•Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VCC.
INSTRUCTION REGISTER
In accordance with the IEEE-1149.1 standard, the IDT72V71643 uses
public instructions. The IDT72V71643 JTAG Interface contains a two-bit
instruction register. Instructions are serially loaded into the instruction register
from the TDI when the TAP Controller is in its shifted-IR state. Subsequently,
the instructions are decoded to achieve two basic functions: to select the test data
register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and TDO during
data register scanning.
Value Instruction
00 EXTEST
11 BYPASS
01 or 10 SAMPLE/PRELOAD
TEST DATA REGISTER
As specified in IEEE-1149.1, the IDT72V71643 JTAG Interface contains
two test data registers:
•The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the IDT72V71643 core
logic.
•The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit
path from TDI to its TDO. The IDT72V71643 boundary scan register bits are
shown in Table 10. Bit 0 is the first bit clocked out. All three-state enable bits are
active high.
JTAG Instruction Register Decoding
