7
COMMERCIAL TEMPERATURE RANGE
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RXn channel m data comes from the
TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero and the device must be in regular switch mode
(DR3-0 = 0x0, 0x1 or 0x2).
OUTPUT ENABLE INDICATION
The IDT72V71643 has the capability to indicate the state of the outputs (active
or three-state) by enabling the Output Enable Indication (OEI) in the control
register. In the OEI mode however, only half of the output streams are available.
If this same capability is desired with all 32 streams, this can be accomplished
by using two IDT72V71643 devices. In one device, the All Output Enable (AOE)
bit is set to a one while in the other the AOE is set to zero. In this way, one device
acts as the switch and the other as a three-state control device. See Figure 8.
It is important to note if the TSI device is programmed for AOE and the OEI is
also set, the device will be in the AOE mode not OEI.
INITIALIZATION OF THE IDT72V71643
After power up, the IDT72V71643 should be reset. During reset, the internal
registers are put into their default state and all TX outputs are put into three-state.
After reset however, the state of Connection Memory is unknown. As such, the
outputs should be put in high-impedance by holding the ODE low. While the ODE
is low, the microprocessor can initialize the device, program the active paths,
and disable unused outputs by programming the OE bit in Connection Memory.
Once the device is configured, the ODE pin (or OSB bit depending on
initialization) can be switched.
