22
COMMERCIAL TEMPERATURE RANGE
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK
Symbol Parameter Min. Typ. Max. Units
t
FPW
(1)
Frame Pulse Width (ST-BUS
®
, GCI)
Bit rate = 2.048 Mb/s 26 ⎯ 295 ns
Bit rate = 4.096 Mb/s 26 ⎯ 145 ns
Bit rate = 8.192 Mb/s or 16.384 Mb/s 26 ⎯ 65 ns
tFPS
(1)
Frame Pulse Setup time before CLK falling (ST-BUS
®
or GCI) 5 ⎯⎯ns
tFPH
(1)
Frame Pulse Hold Time from CLK falling (ST-BUS
®
or GCI) 10 ⎯⎯ns
t
CP
(1)
CLK Period
Bit rate = 2.048 Mb/s 190 ⎯ 300 ns
Bit rate = 4.096 Mb/s 110 ⎯ 150 ns
Bit rate = 8.192 Mb/s or 16.384 Mb/s 58 ⎯ 70 ns
t
CH
(1)
CLK Pulse Width HIGH
Bit rate = 2.048 Mb/s 85 ⎯ 150 ns
Bit rate = 4.096 Mb/s 50 ⎯ 75 ns
Bit rate = 8.192 Mb/s or 16.384 Mb/s 20 ⎯ 40 ns
t
CL
(1)
CLK Pulse Width LOW
Bit rate = 2.048 Mb/s 85 ⎯ 150 ns
Bit rate = 4.096 Mb/s 50 ⎯ 75 ns
Bit rate = 8.192 Mb/s or 16.384 Mb/s 20 ⎯ 40 ns
tr, tf Clock Rise/Fall Time ⎯⎯10 ns
t
HFPW
(2)
Wide Frame Pulse Width
HCLK = 4.096 MHz 244 ns
HCLK = 8.192 MHz 122 ns
tHFPS
(2)
Frame Pulse Setup Time before HCLK 4 MHz falling 50 ⎯ 150 ns
tHFPH
(2)
Frame Pulse Hold Time from HCLK 4 MHz falling 50 ⎯ 150 ns
tHFPS
(2)
Frame Pulse Setup Time before HCLK 8 MHz rising 45 ⎯ 90 ns
tHFPH
(2)
Frame Pulse Hold Time from HCLK 8 MHz rising 45 ⎯ 90 ns
t
HCP
(2)
HCLK Period
@ 4.096 MHz 244 ns
@ 8.192 MHz 122 ns
tHr, tHf HCLK Rise/Fall Time ⎯⎯10 ns
t
DIF
(2)
Delay between falling edge of HCLK and falling edge of CLK -10 ⎯ 10 ns
NOTES:
1. WFPS Pin = 0.
2. WFPS Pin = 1.
