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HVF9C64_128x72K.fm - Rev. C 3/07 EN
10 ©2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
I
DD
Specifications
Table 10: IDD Specifications and Conditions – 1GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
Parameter/Condition
Symbol
-80E-
800
-667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0 810 765 630 630 mA
Operating one bank active-read-precharge current: I
OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH
between valid commands; Address bus inputs are switching; Data pattern
is same as I
DD4W
I
DD1 990 900 855 810 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2P 63 63 63 63 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus
inputs are stable; Data bus inputs are floating
IDD2Q 450 360 360 315 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
I
DD2N 450 360 360 315 mA
Active power-down current: All device banks open;
t
CK =
t
CK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P 360 270 270 270 mA
Slow PDN exit
MR[12] = 1
90 90 90 90 mA
Active standby current: All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD3N 540 495 405 360 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
DD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
I
DD4W 1,440 1,215 1,125 945 mA
Operating burst read current: All device banks open; Continuous burst
reads; I
OUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
I
DD4R 1,440 1,215 1,125 945 mA
Burst refresh current:
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
I
DD5 2,115 1,935 1,890 1,845 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD663636363mA
Operating bank interleave read current: All device banks
interleaving reads; I
OUT = 0mA; BL = 4, CL = CL (IDD),
AL =
t
RCD (IDD) - 1 ×
t
CK (IDD);
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are stable during deselects; Data bus
inputs are switching
I
DD7 3,015 2,520 2,430 2,340 mA
