MT9HVF6472PKY-40EB1 Datasheet MT9HVF12872KY-40EA1, MT9HVF12872KY-53EA1, MT9HVF12872KY-667A1 | P7-P9

PDF: 09005aef81c9620b/Source: 09005aef81c961ec Micron Technology, Inc., reserves the right to change products or specifications without notice.

HVF9C64_128x72K.fm - Rev. C 3/07 EN

512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM

General Description

The MT9HVF6472(P)K and MT9HVF12872(P)K DDR2 SDRAM modules are high-speed,

CMOS, dynamic random-access 512MB and 1GB memory modules organized in a

x72 configuration. DDR2 SDRAM modules use internally configured 4-bank (512Mb) or

8-bank (1Gb) DDR2 SDRAM devices.

DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-

tion. The double data rate architecture is essentially a 4n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR2 SDRAM module effectively consists of a single

4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-

sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

device during READs and by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data for WRITEs.

DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands are registered at every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both edges of DQS, as well as to both

edges of CK.

DDR2 SDRAM modules operate in registered mode, where the command/address input

signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM

devices on the following rising clock edge (data access is delayed by one clock cycle). A

phase-lock loop (PLL) on the module receives and re-drives the differential clock signals

(CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address,

command, control, and clock signal loading by isolating DRAM from the system

controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the

JEDEC clock reference board. Registered mode will add one clock cycle to CL.

Serial Presence-Detect Operation

DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is

implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains

256 bytes. The first 128 bytes are programmed by Micron to identify the module type and

various SDRAM organizations and timing parameters. The remaining 128 bytes of

storage are available for use by the customer. System READ/WRITE operations between

the master (system logic) and the slave EEPROM device occur via a standard I

C bus

using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which

provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V

SS on the

module, permanently disabling hardware write protect.

PDF: 09005aef81c9620b/Source: 09005aef81c961ec Micron Technology, Inc., reserves the right to change products or specifications without notice.

HVF9C64_128x72K.fm - Rev. C 3/07 EN

512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM

Electrical Specifications

Stresses greater than those listed in Table 7 may cause permanent damage to the

module. This is a stress rating only, and functional operation of the module at these or

any other conditions above those indicated in each device’s data sheet is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

Notes: 1. Refresh rate is required to double when 85°C < T

≤ 95°C.

2. For further information, refer to technical note TN-00-08: Thermal Applications, available

on Micron’s Web site.

Input Capacitance

Micron encourages designers to simulate the performance of the module to achieve

optimum values. Simulations are significantly more accurate and realistic than a gross

estimation of module capacitance when inductance and delay parameters associated

with trace lengths are used in simulations. JEDEC modules are currently designed using

simulations to close timing budgets.

Component AC Operating Specifications

Recommended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron’s Web site. Module speed grades

correlate with component speed grades as shown in Table 8.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

DD/VDDQ

VDD/VDDQ supply voltage relative to VSS

–0.5 +2.3 V

IN, VOUT

Voltage on any pin relative to VSS

–0.5 +2.3 V

Input leakage current; Any input 0V ≤ VIN ≤ VDD;

REF input 0V ≤ VIN ≤ 0.95V (All other pins not under

test = 0V)

Command/address

RAS#, CAS#, WE#, S#,

CKE, ODT, BA

–5 +5 µA

CK, CK#

–250 +250

–5 +5

IOZ

Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and

ODT are disabled

DQ, DQS, DQS#

–5 +5 µA

VREF

VREF leakage current; VREF = valid VREF level

–18 +18 µA

Module ambient operating temperature Commercial

0+70°C

Industrial

–40 +85 °C

DDR2 SDRAM component case operating

temperature

Commercial

0+85°C

Industrial

–40 +95 °C

Table 8: Module and Component Speed Grades

Module Speed Grade Component Speed Grade

-80E -25E

-800 -25

-667 -3

-53E -37E

-40E -5E

PDF: 09005aef81c9620b/Source: 09005aef81c961ec Micron Technology, Inc., reserves the right to change products or specifications without notice.

HVF9C64_128x72K.fm - Rev. C 3/07 EN

512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM

Specifications

IDD Specifications

Table 9: IDD Specifications and Conditions – 512MB

Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the

512Mb (64 Meg x 8) component data sheet

Parameter/Condition Symbol

-80E

-800 -667 -53E -40E Units

Operating one bank active-precharge current:

CK =

CK (IDD),

RC =

RC (IDD),

RAS =

RAS MIN (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data bus inputs are

switching

DD0 900 810 720 720 mA

Operating one bank active-read-precharge current: IOUT = 0mA;

BL = 4, CL = CL (IDD), AL = 0;

CK =

CK (IDD),

RC =

RC (IDD),

RAS =

RAS MIN (IDD),

RCD =

RCD (IDD); CKE is HIGH, S# is HIGH

between valid commands; Address bus inputs are switching; Data

pattern is same as I

DD4W

DD1 1,035 945 855 810 mA

Precharge power-down current: All device banks

idle;

CK =

CK (IDD); CKE is LOW; Other control and address bus inputs

are stable; Data bus inputs are floating

DD2P 63 63 63 63 mA

Precharge quiet standby current: All device banks idle;

CK =

CK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus

inputs are stable; Data bus inputs are floating

IDD2Q 450 405 360 315 mA

Precharge standby current: All device banks idle;

CK =

CK (IDD); CKE

is HIGH, S# is HIGH; Other control and address bus inputs are switching;

Data bus inputs are switching

IDD2N 495 450 405 360 mA

Active power-down current: All device banks open;

CK =

CK (IDD); CKE is LOW; Other control and address

bus inputs are stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0

DD3P 360 315 270 225 mA

Slow PDN exit

MR[12] = 1

108 108 108 108 mA

Active standby current: All device banks open;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Other control and address bus inputs are switching;

Data bus inputs are switching

IDD3N 630 585 495 405 mA

Operating burst write current: All device banks open; Continuous

burst writes; BL = 4, CL = CL (I

DD), AL = 0;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data bus inputs are

switching

DD4W 1,755 1,530 1,260 1,035 mA

Operating burst read current: All device banks open; Continuous

burst reads; I

OUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data bus inputs are

switching

DD4R 1,845 1,620 1,305 1,035 mA

Burst refresh current:

CK =

CK (IDD); REFRESH command at every

RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are

switching

DD5 2,070 1,620 1,530 1,485 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and

address bus inputs are floating; Data bus inputs are floating

IDD663636363mA

Operating bank interleave read current: All device banks

interleaving reads; I

OUT= 0mA; BL = 4, CL = CL (IDD), AL =

RCD (IDD)-

1×

CK (IDD);

CK =

CK (IDD),

RC =

RC (IDD),

RRD =

RRD (IDD),

RCD =

RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are stable during deselects; Data bus inputs are switching

DD7 2,700 2,160 2,025 1,980 mA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

MT9HVF6472PKY-40EB1

Mfr. #:

Buy MT9HVF6472PKY-40EB1

Manufacturer:

Micron

Description:

MOD DDR2 SDRAM 512MB 244MRDIMM

Lifecycle:

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MT9HVF6472PKY-40EB1

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