ADF4154 Data Sheet
Rev. C | Page 16 of 24
REGISTER DEFINITIONS
N-Divider Register, R0
The on-chip N-divider register is programmed by setting
R0 [1, 0] to [0, 0]. Table 7 shows the input data format for
programming this register.
9-Bit RF N Value (INT)
These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor (see
Equation 1).
12-Bit RF FRAC Value
These 12 bits control what is loaded as the FRAC value into the
fractional interpolator. This value helps determine the overall
feedback division factor (see Equation 1). The FRAC value must
be less than the value loaded into the MOD register.
Fast Lock
Setting the part to logic high enables fast-lock mode. To use fast
lock, the required time value for wide bandwidth mode must be
loaded into the R-divider register.
The charge pump current increases from 16× the minimum
current and reverts back to 1× the minimum current after the
time value loaded expires.
See the Fast-Lock Timer and Register Sequences section for
more information.
R-DIVIDER REGISTER, R1
The on-chip R-divider register is programmed by setting
R1 [1, 0] to [0, 1]. Table 8 shows the input data format for
programming this register.
Load Control
When this bit is set to logic high, the value being programmed
in the modulus is not loaded into the modulus. Instead, it sets
the fast-lock timer. The value of the fast-lock timer divided by
f
PFD
is the amount of time the PLL stays in wide bandwidth mode.
MUXOUT
The on-chip multiplexer is controlled by R1 [22 ... 20] on the
ADF4154. Table 8 shows the truth table.
Digital Lock Detect
The digital lock detect output goes high if there are 40 successive
PFD cycles with an input error of less than 15 ns. It stays high
until a new channel is programmed or until the error at the
PFD input exceeds 30 ns for one or more cycles. If the loop
bandwidth is narrow compared with the PFD frequency, the
error at the PFD inputs may drop below 15 ns for 40 cycles
around a cycle slip. Therefore, the digital lock detect may briefly,
and falsely, go high until the error exceeds 30 ns. In this case, the
digital lock detect is reliable only as a loss-of-lock detector.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RF
IN
to the PFD input. Operating at CML levels, the
prescaler uses the clock from the RF input stage and divides it
down for the counters. The prescaler is based on a synchronous
4/5 core. When it is set to 4/5, the maximum RF frequency
allowed is 2 GHz. Therefore, when operating the ADF4154 with
frequencies greater than 2 GHz, the prescaler must be set to 8/9.
The prescaler limits the INT value as follows:
With P = 4/5, N
MIN
= 31
With P = 8/9, N
MIN
= 91
The prescaler can also influence the phase noise performance.
If INT < 91, a prescaler of 4/5 should be used. For applications
where INT > 91, a prescaler of 8/9 should be used for optimum
noise performance (see Table 8).
4-Bit R Value
The 4-bit R value allows the input reference frequency (REF
IN
)
to be divided down to produce the reference clock for the PFD.
Division ratios from 1 to 15 are allowed.
12-Bit Interpolator Modulus Value/Fast-Lock Timer
Depending on the value of the load control bit, Bits DB13:DB2
can either be used to set the modulus or the fast-lock timer value.
When the load control bit (DB23) is set to 0, the required
modulus can be programmed in the R-divider register
(DB13:DB2).
When the load control bit (DB23) is set to 1, the required fast-
lock timer value can be programmed in the R-divider register
(DB13:DB2).
This programmable register sets the fractional modulus, which
is the ratio of the PFD frequency to the channel step resolution
on the RF output. Refer to the RF Synthesizer: A Worked
Example section for more information.
The ADF4154 programmable modulus is double buffered,
meaning that two events must occur before the part can use a
new modulus value. The first event is that the new modulus value
must be latched into the device by writing to the R-divider register,
and the second event is that a new write must be performed on
the N-divider register. Therefore, whenever the modulus value
is updated, the N-divider register must be written to so that the
modulus value is loaded correctly.
CONTROL REGISTER, R2
The on-chip control register is programmed by setting R2 [1, 0]
to [0, 1]. Table 9 shows the input data format for programming
this register.
RF Counter Reset
DB2 is the RF counter reset bit for the ADF4154. When this bit
is set to 1, the RF synthesizer counters are held in reset. For
normal operation, this bit should be set to 0.
