Data Sheet ADF4154
Rev. C | Page 3 of 24
SPECIFICATIONS
AV
DD
= DV
DD
= SDV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm
referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C.
Table 1.
Parameter B Version Unit Test Conditions/Comments
RF CHARACTERISTICS (3 V)
See
Figure 15 for the input circuit.
RF Input Frequency (RF
IN
)
1
0.5/4.0 GHz min/max −8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 400 V/µs.
1.0/4.0 GHz min/max −10 dBm/0 dBm min/max.
REFERENCE CHARACTERISTICS
See
Figure 14 for input circuit.
REF
IN
Input Frequency
1
10/250 MHz min/max For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave,
slew rate > 25 V/µs.
REF
IN
Input Sensitivity 0.7/AV
DD
V p-p min/max Biased at AV
DD
/2.
2
REF
IN
Input Capacitance 10 pF max
IN
PHASE DETECTOR
Phase Detector Frequency
3
32 MHz max
CHARGE PUMP
I
CP
Sink/Source
Programmable. See
Table 5.
High Value 5 mA typ With R
SET
= 5.1 kΩ.
Low Value 312.5 µA typ
Absolute Accuracy 2.5 % typ With R
SET
= 5.1 kΩ.
R
SET
Range 2.7/10 kΩ min/max
I
CP
Three-State Leakage Current 1 nA typ Sink and source current.
Matching 2 % typ 0.5 V < V
CP
< V
P
− 0.5 V.
I
CP
vs. V
CP
2 % typ 0.5 V < V
CP
< V
P
− 0.5 V.
I
CP
vs. Temperature 2 % typ V
CP
= V
P
/2.
LOGIC INPUTS
V
INH
, Input High Voltage 1.4 V min
V
INL
, Input Low Voltage 0.6 V max
I
INH
/I
INL
, Input Current ±1 µA max
C
IN
, Input Capacitance 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V.
V
OL
, Output Low Voltage 0.4 V max I
OL
= 500 µA.
POWER SUPPLIES
AV
DD
2.7/3.3 V min/V max
DV
DD
, SDV
DD
AV
DD
V
P
AV
DD
/5.5 V min/V max
I
DD
24 mA max 20 mA typical.
Low Power Sleep Mode 1 µA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PN
SYNTH
)
4
−220 dBc/Hz typ PLL loop BW = 500 kHz.
Measured at 100 kHz offset.
1_f
5
10 kHz offset; normalized to 1GHz.
Phase Noise Performance
6
@ VCO output.
1750 MHz Output
7
−102 dBc/Hz typ @ 1 kHz offset, 26 MHz PFD frequency.
1
Use a square wave for frequencies below f
MIN
.
2
AC coupling ensures AV
DD
/2 bias. See Figure 14 for a typical circuit.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(F
PFD
). PN
SYNTH
= PN
TOT
− 10 log(F
PFD
) − 20 log(N).
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, F
RF
,
and at a frequency offset f is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(F
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6
The phase noise is measured with the EVAL-ADF4154EB1 and the HP8562E spectrum analyzer.
7
f
REFIN
= 26 MHz, f
PFD
= 26 MHz, offset frequency = 1 kHz, RF
OUT
= 1750 MHz, loop B/W = 20 kHz, lowest noise mode.
