ADF4154 Data Sheet
Rev. C | Page 6 of 24
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
ADF4154
TOP VIEW
(Not to Scale)
AGND
4
RF
IN
B
5
RF
IN
A
6
AV
DD
7
REF
IN
8
LE
DATA
CLK
SDV
DD
DGND
13
12
11
10
R
SET
1
CP
2
CPGND
3
V
P
DV
DD
MUXOUT
16
15
14
9
04833-002
Figure 3. TSSOP Pin Configuration
04833-003
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11
SDV
DD
CPGND
AGND
2
AGND
RF
IN
B
5
RF
IN
A
7
AV
DD
6
AV
DD
8
REF
IN
9
DGND
10
DGND
19
R
SET
20
CP
18 V
P
17
DV
DD
16
DV
DD
ADF4154
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP LFCSP Mnemonic Description
1 19 R
SET
Set Resistor. Connecting a resistor between this pin and ground sets the maximum charge pump
output current. The relationship between I
CP
and R
SET
is
SET
CPmax
R
I
5.25
where R
SET
= 5.1 kΩ and I
CPmax
= 5 mA.
2 20 CP
Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which in turn
drives the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RF
IN
B
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF (see Figure 15).
6 5 RF
IN
A Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6, 7 AV
DD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed
as close as possible to this pin. AV
DD
has a value of 3 V ± 10%. AV
DD
must have the same voltage as DV
DD
.
8 8 REF
IN
Reference Input. This CMOS input has a nominal threshold of V
DD
/2 and an equivalent input resistance of
100 kΩ (see Figure 14). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 SDV
DD
Σ-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to
this pin. SDV
DD
has a value of 3 V ± 10%. SDV
DD
must have the same voltage as DV
DD
.
11 12 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a
high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
four latches, which is selected by the user via the control bits.
14 15 MUXOUT
Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15 16, 17 DV
DD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DV
DD
has a value of 3 V ± 10%. DV
DD
must have the same
voltage as AV
DD
.
16 18 V
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
N/A EP EPAD Exposed Pad. The exposed pad must be connected to AGND.
