ADF4154BCPZ Datasheet ADF4154BCPZ, ADF4154BRUZ, ADF4154BRUZ-RL7 | P19-P21

ADF4154 Data Sheet

Rev. C | Page 18 of 24

INITIALIZATION SEQUENCE

The following initialization sequence should be followed after

powering up the part:

1. Clear all test modes by writing all 0s to the noise and spur

2. Select the noise and spur mode required for the application

by writing to the noise and spur register. For example, writing

Hex 0003C7 to the part selects low noise mode.

3. Enable the counter reset in the control register by writing a

1 to DB2 and selecting the required settings in the control

4. Load the R-divider register (with the load control bit [DB23]

set to 0).

5. Load the N-divider register.

6. Disable the counter reset by writing a 0 to DB2 in the

control register.

The part should now lock to the set frequency.

RF SYNTHESIZER: A WORKED EXAMPLE

This equation governs how the synthesizer should be

programmed.

OUT

= [INT + (FRAC/MOD)] × [f

PFD

] (3)

where:

OUT

is the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

MOD is the modulus.

The PFD frequency can be calculated as follows:

PFD

= [REF

× (1 = D)/R] (4)

where:

REF

is the reference frequency input.

D is the value of the RF REF

doubler bit.

R is the RF reference division factor.

For example, in a GSM 1800 system, where a 1.8 GHz RF

frequency output (RF

OUT

) is required, a 13 MHz reference

frequency input (REF

) is available and a 200 kHz channel

resolution (f

RES

) is required on the RF output.

RES

fREFMOD /

65kHz200MHz/13

==MOD

From Equation 4,

PFD

= [13 MHz × (1 + 0)/1] = 13 MHz (5)

( )

65FRACINTMHz13GHz8.1 +×=

(6)

where:

INT is 138.

FRAC is 30.

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REF

) available and the channel resolution (f

RES

) required at

the RF output. For example, a GSM 1800 system using a 13 MHz

REF

sets the modulus to 65, resulting in meeting the required

RF output resolution (f

RES

) of 200 kHz (13 MHz/65).

REFERENCE DOUBLER AND REFERENCE DIVIDER

The on-chip reference doubler allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency, which in turn improves the noise performance of the

system. For example, doubling the PFD frequency usually

results in an improvement in noise performance of 3 dB. It is

important to note that the PFD cannot operate with frequencies

greater than 32 MHz due to a limitation in the speed of the Σ-Δ

circuit of the N-divider.

12-BIT PROGRAMMABLE MODULUS

Unlike most fractional-N PLLs, the ADF4154 allows the user

to program the modulus over a 12-bit range. Therefore, several

configurations of the ADF4154 are possible for an application by

varying the modulus value, the reference doubler, and the 4-bit

R-counter.

For example, consider an application that requires a 1.75 GHz

RF and a 200 kHz channel step resolution. The system has a

13 MHz reference signal.

One possible setup is feeding the 13 MHz REF

directly into

the PFD and programming the modulus to divide by 65, which

results in the required 200 kHz resolution.

Another possible setup is using the reference doubler to create a

26 MHz input frequency from the 13 MHz REF

signal. The

26 MHz signal is then fed into the PFD, which programs the

modulus to divide by 130. This setup also results in 200 kHz

resolution, plus it offers superior phase noise performance

compared with the previous setup.

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC and

GSM 1800 standards, the programmable modulus is a huge

benefit. The PDC requires a 25 kHz channel step resolution,

whereas the GSM 1800 requires a 200 kHz channel step

resolution. A 13 MHz reference signal could be fed directly to

the PFD. The modulus would be programmed to 520 when in

PDC mode (13 MHz/520 = 25 kHz). The modulus would be

reprogrammed to 65 for GSM 1800 operation (13 MHz/65 =

200 kHz). It is important that the PFD frequency remains con-

stant (13 MHz). By keeping the PFD constant, the user can

design a one-loop filter that can be used in both setups without

running into stability issues. The ratio of the RF frequency to

the PFD frequency affects the loop design. By keeping this

relationship constant, the same loop filter can be used in both

applications.

SPURIOUS OPTIMIZATION AND FAST LOCK

The ADF4154 can be optimized for low spurious signals by

using the noise and spur register. However, to achieve fast-lock

time, a wider loop bandwidth is needed. Note that a wider loop

Data Sheet ADF4154

Rev. C | Page 19 of 24

bandwidth can lead to notable spurious signals, which cannot

be reduced significantly by the loop filter.

Using the fast-lock feature can achieve the same fast-lock time

as the noise and spur register, but with the advantage of lower

spurious signals because the final loop bandwidth is reduced by

a quarter.

FAST-LOCK TIMER AND REGISTER SEQUENCES

If the fast-lock mode is used, a timer value needs to be loaded

into the PLL to determine the time spent in wide bandwidth

mode.

When the load control bit is set to 1, the timer value is loaded

via the 12-bit modulus value. To use fast lock, the PLL must be

written to in the following sequence:

1. Load the R-divider register with DB23 = 1 and the chosen

fast-lock timer value (DB13 to DB2) instead of the

modulus. Note that the duration that the PLL remains in

wide bandwidth is equal to the fast-lock timer/f

PFD

2. Load the noise and spur register.

3. Load the control register.

4. Load the R-divider register with DB23 = 0 and MUXOUT

= 110 (DB22 to DB20). This sets the fast-lock switch to

appear at the MUXOUT pin. All the other needed

parameters, including the modulus, also need to be loaded.

5. Load the N-divider register, including fast lock = 1 (DB23),

to activate fast-lock mode.

After this procedure is complete, the user need only repeat

Step 5 to invoke fast lock for subsequent frequency jumps.

FAST LOCK: AN EXAMPLE

If a PLL has reference frequencies of 13 MHz and f

PFD

= 13 MHz

and a required lock time of 50 µs, the PLL is set to wide bandwidth

for 40 µs.

If the time period set for the wide bandwidth is 40 µs, then

Fast-Lock Timer Value = Time in Wide Bandwidth × f

PFD

Fast-Lock Timer Value = 40 µs × 13 MHz = 520

Therefore, 520 must be loaded into the R-divider register in

Step 1 of the sequence described in the Fast-Lock Timer and

FAST LOCK: LOOP FILTER TOPOLOGY

To use fast-lock mode, an extra connection from the PLL to the

loop filter is needed. The damping resistor in the loop filter

must be reduced to ¼ of its value while in wide bandwidth

mode. This is required because the charge pump current is

increased by 16 while in wide bandwidth mode, and stability

must be ensured. During fast lock, the MUXOUT pin is shorted

to ground (the fast-lock switch must be programmed to appear

at the MUXOUT pin). The following two topologies can be used:

• Divide the damping resistor (R1) into two values (R1 and

R1A) that have a ratio of 1:3 (see Figure 19).

• Connect an extra resistor (R1A) directly from MUXOUT,

as shown in Figure 19. The extra resistor must be chosen

such that the parallel combination of an extra resistor and

the damping resistor (R1) is reduced to ¼ of the original

value of R1 (see Figure 20).

ADF4154

MUXOUT

R1A

VCO

04833-029

Figure 19. Fast-Lock Loop Filter Topology—Topology 1

ADF4154

MUXOUT

R1R1A

VCO

04833-030

Figure 20. Fast-Lock Loop Filter Topology—Topology 2

SPUR MECHANISMS

The following section describes three spur mechanisms that can

arise when using a fractional-N synthesizer and how to minimize

them in the ADF4154.

Fractional Spurs

The fractional interpolator in the ADF4154 is a third-order Σ-Δ

modulator (SDM) with a modulus MOD that is programmable

to an integer value between 2 and 4095. In low spur mode

(dither enabled), the minimum allowed value of MOD is 50.

The SDM is clocked at the PFD reference rate (f

PFD

) that allows

PLL output frequencies to be synthesized at a channel step

resolution of f

PFD

/MOD.

In low noise mode and low noise and spur mode (dither off),

the quantization noise from the Σ-Δ modulator appears as frac-

tional spurs. The interval between spurs is f

PFD

/L, where L is the

repeat length of the code sequence in the digital Σ-Δ modulator.

For the third-order modulator used in the ADF4154, the repeat

length depends on the value of MOD, as shown in Table 11.

Table 11. Fractional Spurs with Dither Off

Condition (Dither Off)

Repeat

Length

Spur Interval

If MOD is divisible by 2, but not 3 2 × MOD Channel step/2

If MOD is divisible by 3, but not 2 3 × MOD Channel step/3

If MOD is divisible by 6 6 × MOD Channel step/6

Otherwise MOD Channel step

ADF4154 Data Sheet

Rev. C | Page 20 of 24

In low spur mode (dither enabled), the repeat length is

extended to 2

cycles, regardless of the value of MOD, which

makes the quantization error spectrum appear as broadband

noise. This can degrade the in-band phase noise at the PLL

output by as much as 10 dB. Therefore, for lowest noise, dither

off is a better choice, particularly when the final loop BW is low

enough to attenuate even the lowest frequency fractional spur.

Integer Boundary Spurs

Another mechanism for fractional spur creation are interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (as is the case

with fractional-N synthesizers), spur sidebands appear on the

VCO output spectrum at an offset frequency that corresponds

to the beat note or the difference in frequency between an

integer multiple of the reference and the VCO frequency.

These spurs are attenuated by the loop filter and are more

noticeable on channels close to integer multiples of the

reference, where the difference frequency can be inside the loop

bandwidth, thus the name integer boundary spurs.

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. One such

mechanism is feedthrough of low levels of on-chip reference

switching noise through the RF

pin back to the VCO, resulting

in reference spur levels as high as –90 dBc. Care should be

taken in the PCB layout to ensure that the VCO is well

separated from the input reference to avoid a possible feed-

through path on the board.

SPUR CONSISTENCY

When jumping from Frequency A to Frequency B and then

back again using fractional-N synthesizers, the spur levels often

differ each time Frequency A is programmed. However, in the

ADF4154, the spur levels on any particular channel are always

consistent.

FILTER DESIGN—ADIsimPLL

A filter design and analysis program is available to help the user

implement the PLL design. Visit www.analog.com/pll for a free

download of the ADIsimPLL software. The software designs,

simulates, and analyzes the entire PLL frequency and time

domain response. Various passive and active filter architectures

are allowed.

INTERFACING

The ADF4154 has a simple, SPI®-compatible serial interface for

writing to the device. SCLK, SDATA, and LE control the data

transfer. When LE (latch enable) is high, the 22 bits that have

been clocked into the input register on each rising edge of

SCLK are transferred to the appropriate latch. See Figure 2 for

the timing diagram and Ta ble 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

909 kHz or one update every 1.1 µs.

ADuC812 Interface

Figure 21 shows the interface between the ADF4154 and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA set to 0. To initiate the operation, bring the

I/O port driving LE low. Each latch of the ADF4154 requires a

24-bit word, which is accomplished by writing three 8-bit bytes

from the MicroConverter to the device. After the third byte is

written, the LE input should be brought high to complete the

transfer.

When operating in the mode described, the maximum

SCLOCK rate of the ADuC812 is 4 MHz. This means that the

maximum rate at which the output frequency can be changed is

180 kHz.

ADuC812 ADF4154

SCLOCK

SCLK

SDATA

MUXOUT

(LOCK DETECT)

MOSI

I/O PORTS

04833-024

Figure 21. ADuC812-to-ADF4154 Interface

ADSP-21xx Interface

Figure 22 shows the interface between the ADF4154 and the

ADSP-21xx digital signal processor. As discussed previously, the

ADF4154 requires a 24-bit serial word for each latch write. The

easiest way to accomplish this using a device in the ADSP-21xx

family is to use the autobuffered transmit mode of operation

with alternate framing. This provides a means for transmitting

an entire block of serial data before an interrupt is generated.

Set up the word length for eight bits and use three memory

locations for each 24-bit word. To program each 24-bit latch,

store each of the three 8-bit bytes, enable the autobuffered

mode, and write to the transmit register of the DSP. This last

operation initiates the autobuffered transfer.

ADSP-21xx ADF4154

SCLOCK

SCLK

ATA

MUXOUT

(LOCK DETECT)

TFS

I/O FLAGS

04833-025

Figure 22. ADSP-21xx-to-ADF4154 Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADF4154BCPZ

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Phase Locked Loops - PLL Fractional-N Freq Synthesizer

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