L6722TR Datasheet L6722TR, L6722 | P16-P18

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6 Current sharing loop and current reading L6722

16/34

6 Current sharing loop and current reading

L6722 embeds two separate Current-Reading circuitries used to perform Current-Sharing and

OCP through ISENx pins and Voltage-Positioning through CS+ and CS- pins (See Section 7).

Current-sharing control-loop and connections are reported in Figure 6: the current read through

the I

SENx

pins is converted into a current I

INFOx

proportional to the current delivered by each

phase and the information about the average current I

AVG

= ΣI

INFOx

/ 3 is internally built into the

device. The error between the read current I

INFOx

and the reference I

AVG

is then converted into

a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by

the voltage error amplifier in order to equalize the current carried by each phase.

The current flowing trough each phase is read using the voltage drop across the low-side

mosfets R

dsON

or across a sense resistor in its series and it is internally converted into a

current. The trans-conductance ratio is issued by the external resistor R

ISEN

placed outside the

chip between I

SENx

and the reading point (usually the LS mosfet Drain).

The current sense circuit tracks the current information for a time T

TRACK

centered in the

middle of the LS conduction time and holds the tracked information during the rest of the

period. The current that flows from the I

SENx

pin is the current information used by the device to

perform current sharing and OCP and it is given by:

where R

dsON

is the ON resistance of the low side mosfet and R

ISEN

is the trans-conductance

resistor connected between the ISENx pins and the LS Drain; I

PHASEx

is the current carried by

the relative phase and I

INFOx

is the current information signal reproduced internally.

ISENx

is designed according to the Over Current Protection: see Section 9.6 for details.

Caution: Asymmetries in the R

ISENx

values are allowed in order to create intentional current-unbalance

so that one phase can carry higher currents or support different cooling. To increase the current

in any of the phases, the value of the related R

ISEN

can be slightly increased starting from the

theoretical value extracted from the above reported relationships. Start from the coolest phase

first to get the thermal balance.

Figure 6. Current sharing loop and current reading connections

ISENx

dsON

ISEN

-----------------

PHASEx

⋅ I

INFO

INFO1

PWM1 Out

From EA

INFO2

AVG

PWM2 Out

INFO3

PWM3 Out

AVG

ISENx

LGATEx

PHASEx

ISEN

ISENx

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L6722 7 Output voltage positioning

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7 Output voltage positioning

Output voltage positioning is performed by programming the external resistor divider and by

correctly designing Droop Function and Offset to the reference (Optional). The output voltage is

then driven by the following relationship (See Figure 7):

Both DROOP and OFFSET function can be disabled: see Section 7.1 and Section 7.2 for

details.

L6722 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any

additional external components. In this way, the output voltage programmed is regulated

between the remote buffer inputs compensating for board and connector losses. The device

senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated

voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN

pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and

guarded by a power plane results in common mode coupling for any picked-up noise.

When regulating output voltages higher than the reference, it is possible to insert a resistor

divider between FBR, FBG and the regulated voltage as reported in Figure 7. In this case it is

important for the external divider to have a value negligible with respect to the remote buffer

impedance that has 64k resistors.

Figure 7. Voltage positioning

7.1 Offset and margining-mode (optional)

Positive / negative offset can be added to the programmed reference by connecting proper

network resistor between the REF_OUT and REF_IN pins. In this way is possible to manage

margining-mode by adding small offsets (positive or negative) to the regulated voltage, in order

to test the loading-circuitry in different operative conditions to check for the reliability of the

system designed.

Referring to Figure 8, a constant current (I

=12µA) is sourced from the REF_IN pin as soon

as the device is enabled. By correctly designing R

OS1

and R

OS2

, positive and negative offset

may be added to the reference voltage according to the status of the control signals M1 and

M2. Different operating conditions can be then considered:

OUT

Ref()

R1 R2+

----------------------

⋅=

To Vout

(Remote Sense)

DROOP

Ref

FB COMP

VSEN

64k

FBR FBG

64k

REF_INREF_OUT

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7 Output voltage positioning L6722

18/34

Figure 8. Offset definition (margin mode)

● No Offset (M1=1; M2=0)

● Positive Margin (M1=0; M2=0)

● Negative Margin (M1=0; M2=1)

Offset resistors may be simply defined as follow

where V

TA RG ET-P OS

and V

TARGET-NEG

are the target voltages for positive and negative margin

mode.

Offset current is always sourced from REF_IN pin: to avoid having steps during soft-start, the

introduction of C

is required. The resulting time-constant need to be negligible with respect to

the soft-start time as well as long enough to smooth the initial step. Typical values are in the

range of few tens / hundreds of nF.

Offset function can be easily disabled by shorting REF_IN and REF_OUT together.

Warning: Maximum offset must be limited to less than 200mV to avoid setting the OVP protection

resulting in a maximum +25% margin.

7.2 Droop function (optional)

This method "recovers" part of the drop due to the output capacitor ESR in the load transient,

introducing a dependence of the output voltage on the load current: a static error proportional to

the output current causes the output voltage to vary according to the sensed current.

Figure 9 shows the Current Sense Circuit used to implement the Droop Function. The current

flowing across the three inductors is read through the R

- C

filter across CS+ and CS- pins.

programs a transconductance gain and generates a current I

proportional to the average

of the currents of the three phases. The current I

is then mirrored and, multiplied by three,

sourced by the FB pin (I

DROOP

). R

gives the final gain to program the desired load-line slope.

Ref

REF_INREF_OUT

OS1

OS2

To Vout

(Remote Sense)

DROOP

FB COMP VSEN

64k

FBR FBG

64k

REFIN

Ref I

OS1

⋅+=

REFIN

Ref I

OS1

⋅+()

OS2

OS1

----------------------------------

⋅=

OS1

TARGET POS–

Ref–

---------------------------------------------------------= R

OS2

OS1

TARGET POS–

TARGET NEG–

–

----------------------------------------------------------------------------------------

⋅=

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L6722TR

Mfr. #:

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Manufacturer:

STMicroelectronics

Description:

Switching Controllers 3 Phase Controller

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L6722TR

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