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L6722TR

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L6722 7 Output voltage positioning
19/34
Time constant matching between the inductor (L / DCR) and the current reading filter
( ) is required to implement a real equivalent output impedance of the system so
avoiding over and/or under shoot of the output voltage as a consequence of a load transient. In
fact, considering the scheme reported on Figure 9, it is possible to observe that:
By applying the time constant matching concept, it results:
=>
The device forces I
DROOP
= I
CS
x 3, proportional to the read current, into the feedback resistor
R
FB
implementing the load regulation dependence. The output characteristic vs. load current is
then given by (Offset disabled):
Where R
LL
is the resulting load-line resistance implemented by the system.
The whole power supply can be then represented by a "real" voltage generator with an
equivalent output resistance R
LL
and a voltage value of VID.
R
FB
resistor can be then designed according to the R
LL
specifications as follow:
Warning: Droop function is operational for output voltages up to 1.8V.
Caution: Droop function is optional, in case it is not desired, the Current Sense circuit can be tricked so
that the device always read a null current. To do this, it is enough connecting CS+ directly to the
output voltage leaving CS- unconnected. The reaction will keep CS+ and CS- at the same
voltage, always reading a null current and also assuring the FB disconnection protection to be
effective. To aovid setting the FB-disconnection protection, it is also suggested to connect CS+
to local-V
OUT
through the same resistor divider used as external divider (See Figure 1).
To disable also the FB disconnection protection, CS+ can be directly connected to VSEN or
SGND.
Figure 9. Droop function current reading network
R
PH
C
PH
⋅
S
I
OUT
3
------------
1s L⋅ DCR⁄+
1s R⋅
PH
C⋅
PH
3⁄+
------------------------------------------------------------ -
D
C
R
D
-------
-
⋅⋅=
L
D
CR
-
------------
R
PH
C⋅
PH
3
------------------------------=
I
CS
I
OUT
3
------------
DCR
R
D
-------------
⋅=
O
UT
VID R
FB
I
DROOP
⋅– VID R
FB
DCR
R
D
-------------
I
OUT
⋅⋅– VID R
LL
I
O
U
⋅–== =
R
FB
R
LL
R
D
DCR
-------------
⋅=
L2
L1
L3
DCR1
DCR2
DCR3
C
PH
R
PH
R
PH
R
PH
R
D
PHASE3
PHASE2
PHASE1
V
OUT
I
CS
CS+ CS- FB
I
DROOP
x 3
R
F
C
F
R
FB
COMP
L2
L1
L3
DCR1
DCR2
DCR3
PHASE3
PHASE2
PHASE1
V
OUT
I
CS
CS+ CS- FB
I
DROOP
x 3
R
F
C
F
R
FB
COMP
Droop Function Enabled Droop Function Disabled
R
1
R
2
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
7 Output voltage positioning L6722
20/34
7.3 Maximum duty cycle limitation
To provide proper time for current-reading in order to equalize the current carried by each
phase, the device implements a duty-cycle limitation. This limitation is not fixed but it is linearly
variable with the current delivered to the load as follow:
Duty Cycle limitation is variable with the delivered current to provide fast load transient
response at light load as well as assuring robust over-current protection.
Figure 10 shows the maximum output voltage that the device is able to regulate considering the
T
ON
limitation imposed by the previous relationship. If the desired output characteristic crosses
the limited-T
ON
maximum output voltage, the output resulting voltage will start to drop after the
cross-point. In this case, the output voltage starts to decrease following the resulting
characteristic (dotted in Figure 10) until UVP is detected or anyway until I
ISENx
= 35µA.
Figure 10. Maximum duty-cycle limitation
T
ON max()
0.80 T
SW
I
ISENx
0µA=⋅
0.40 T
SW
I
ISENx
35µ
A
=⋅
⎩
⎨
⎧
=
V
OUT
0.40 V
IN
Maximum Output Voltage
0.80 V
IN
I
OCP
= 3 x I
OCPx
(I
ISENx
= 35µA)
I
OUT
V
OUT
0.40 V
IN
Limited T
ON
0.80 V
IN
I
OCP
= 3 x I
OCPx
(I
ISENx
= 35µA)
I
OUT
Desired output Char.
UVP Threshold
Resulting Output Char.
Limted-T
ON
Output Char.
Limted-T
ON
Output Char.
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L6722 8 Soft start
21/34
8 Soft start
L6722 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents
to be required to the input power supply. The device increases the reference from zero up to
the programmed value in 2048 clock periods and the output voltage increases accordingly with
closed loop regulation. At the end of the digital Soft-Start, PGOOD signal is set free.
Protections are active during this phase; Under Voltage is enabled when the reference voltage
reaches 0.6V while Over Voltage is always enabled with a threshold dependent on the selected
Operative Mode
The device implements Soft-Start only when all the power supplies are above their own turn-on
thresholds and the INH pin is set free.
8.1 Low-side-less startup for pre-bias output
To manage pre-biased output start-up and in order to avoid any kind of negative undershoot
and dangerous return from the load, L6722 performs a special sequence in enabling LS driver
to switch: during the soft-start phase, the LS driver results disabled (LS=OFF) until the HS
starts to switch. This avoid the dangerous negative spike on the output voltage that can happen
if starting over a pre-biased output (See Figure 11).
This particular feature of the device masks the LS turn-on only from the control-loop point of
view: protections are still allowed to turn-on the ls mosfet in case of over-voltage if needed.
Figure 11. low-side-less startup
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L6722TR

Mfr. #:
Buy L6722TR
Manufacturer:
STMicroelectronics
Description:
Switching Controllers 3 Phase Controller
Lifecycle:
New from this manufacturer.
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