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L6722 2 Pins description and connection diagrams
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23
OSC / INH /
FLT
Three functional pin:
OSC: It allows programming the switching frequency F
SW
of each
channel: the equivalent switching frequency at the load side results in
being tripled.
Frequency is programmed according to the resistor connected from the
pin vs. SGND or VCC with a gain of 4kHz/µA (see relevant section for
details). Leaving the pin floating programs a switching frequency of
100kHz per phase (300kHz on the load).
INH: Forced low, the device stops operations with all mosfets OFF: all the
protections are disabled except for Preliminary over voltage. It resets the
device from any latching condition.
FLT: The pin is forced high (5V) to signal an OVP FAULT: to recover from
this condition, cycle VCC or the OSC pin. See Section 10 for details.
24 N.C. Not Internally Bonded.
25 REF_IN
REF
rence INput for the regulation. Connect directly or through a resistor
to the REF_OUT pin. See Section 7.1 for details.
26 REF_OUT
REF
rence OUTput. Connect directly or through a resistor to the REF_IN
pin. See Section 7.1 for details.
27, 28 N.C. Not Internally Bonded.
29 SGND
All the internal references are referred to this pin. Connect to the PCB
Signal Ground.
30 FBR
Remote Buffer Non Inverting Input.
Connect to the positive side of the load to perform remote sense.
See Section 12 for proper layout of this connection.
31 FBG
Remote Buffer Inverting Input.
Connect to the negative side of the load to perform remote sense.
See Section 12 for proper layout of this connection.
32 to 34
ISEN3
to
ISEN1
LS Current Sense Pins.
These pins are used for current balance phase-to-phase as well as for the
system OCP. Connect through a resistor Rg to the relative PHASEx pin.
See Section 6 and Section 9.6 for details.
35 CS+
Droop Current Sense non-inverting input.
Connect through R-C network to the main inductors. See Section 7.1 for
details.
36 CS-
Droop Current Sense inverting input.
Connect through resistor R
D
to the main inductors common node. See
Section 7.1 for details.
This pin also monitor the feedback disconnection. See Section 9.4 for
details.
PA D
THERMAL
PA D
Thermal pad connects the Silicon substrate and makes good thermal
contact with the PCB to dissipate the power necessary to drive the
external mosfets.
Connect to the PGND plane with several VIAs to improve thermal
conductivity.
Table 1. Pins description (continued)
Pin# Name Function
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