CY7C1049D
4-Mbit (512 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05474 Rev. *H Revised November 24, 2014
4-Mbit (512 K × 8) Static RAM
Features
■ Pin- and function-compatible with CY7C1049B
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ I
CC
= 90 mA at 10 ns
■ Low CMOS Standby power
❐ I
SB2
= 10 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 36-pin (400-Mil) Molded SOJ package
Functional Description
The CY7C1049D
[1]
is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE
), an active LOW
Output Enable (OE
), and tri-state drivers. Writing to the device is
accomplished by taking Chip Enable (CE
) and Write Enable
(WE
) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip Enable
(CE
) and Output Enable (OE) LOW while forcing Write Enable
(WE
) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH),
the outputs are disabled (OE
HIGH), or during a write operation
(CE
LOW, and WE LOW).
The CY7C1049D is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
The CY7C1049D is suitable for interfacing with processors that
have TTL I/P levels. It is not suitable for processors that require
CMOS I/P levels. Please see Electrical Characteristics on page
4 for more details and suggested alternatives.
For a complete list of related documentation, click here.
14
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
CE
A
A
16
A
17
A
9
A
18
A
10
Logic Block Diagram
Note
1. For guidelines on SRAM system design, refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
