CY7C1049D
Document Number: 38-05474 Rev. *H Page 7 of 15
Switching Characteristics
Over the Operating Range
Parameter
[9]
Description
-10
Unit
Min Max
Read Cycle
t
power
V
CC
(typical) to the First Access
[10]
100 Ps
t
RC
Read Cycle Time 10 ns
t
AA
Address to Data Valid 10 ns
t
OHA
Data Hold from Address Change 3 ns
t
ACE
CE LOW to Data Valid 10 ns
t
DOE
OE LOW to Data Valid 5 ns
t
LZOE
OE LOW to Low Z
[11]
0–ns
t
HZOE
OE HIGH to High Z
[11, 12]
–5ns
t
LZCE
CE LOW to Low Z
[11]
3–ns
t
HZCE
CE HIGH to High Z
[11, 12]
–5ns
t
PU
CE LOW to Power-Up 0 ns
t
PD
CE HIGH to Power-Down 10 ns
Write Cycle
[13, 14]
t
WC
Write Cycle Time 10 ns
t
SCE
CE LOW to Write End 7 ns
t
AW
Address Set-Up to Write End 7 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Set-Up to Write Start 0 ns
t
PWE
WE Pulse Width 7 ns
t
SD
Data Set-Up to Write End 6 ns
t
HD
Data Hold from Write End 0 ns
t
LZWE
WE HIGH to Low Z
[11]
3–ns
t
HZWE
WE LOW to High Z
[11, 12]
–5ns
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
10. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
12. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (c) of Figure 2. Transition is measured when the outputs enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of CE
LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
14. The minimum write cycle time for Write Cycle No. 3 (WE
Controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
CY7C1049D
Document Number: 38-05474 Rev. *H Page 8 of 15
Switching Waveforms
Figure 4. Read Cycle No. 1
[15, 16]
Figure 5. Read Cycle No. 2 (OE Controlled)
[16, 17]
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
Notes
15. Device is continuously selected. OE
, CE = V
IL
.
16. WE
is HIGH for read cycle.
17. Address valid prior to or coincident with CE
transition LOW.
CY7C1049D
Document Number: 38-05474 Rev. *H Page 9 of 15
Figure 6. Write Cycle No. 1 (CE
Controlled)
[18, 19]
Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[18, 19]
Switching Waveforms(continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
ADDRESS
WE
DATA I/O
Notes
18. Data I/O is high impedance if OE
= V
IH
.
19. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
20. During this period the I/Os are in the output state and input signals should not be applied.

CY7C1049D-10VXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4Mb 10ns 512K x 8 Fast Async SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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