CY7C1049D
Document Number: 38-05474 Rev. *H Page 10 of 15
Figure 8. Write Cycle No. 3 (WE
Controlled, OE LOW)
[21, 22]
Switching Waveforms(continued)
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
NOTE
23
Note
21. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
22. The minimum write cycle time for Write Cycle No. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
23. During this period the I/Os are in the output state and input signals should not be applied.
CY7C1049D
Document Number: 38-05474 Rev. *H Page 11 of 15
Ordering Code Definitions
Truth Table
CE OE WE
I/O
0
–I/O
7
Mode Power
H X X High-Z Power-down Standby (I
SB
)
L L H Data Out Read Active (I
CC
)
L X L Data In Write Active (I
CC
)
L H H High-Z Selected, Outputs Disabled Active (I
CC
)
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram
Package Type
Operating
Range
10
CY7C1049D-10VXI 51-85090 36-pin SOJ (Molded) Pb-free Industrial
Please contact your local Cypress sales representative for availability of these parts.
Temperature Range:
I = Industrial
Pb-free
Package Type:
V = 36-pin SOJ (Molded)
Speed: 10 ns
Process Technology: D = C9, 90 nm Technology
Data width: 9 = × 8-bits
Density: 04 = 4-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 - 10 X7 04 D I9 V
CY7C1049D
Document Number: 38-05474 Rev. *H Page 12 of 15
Package Diagram
Figure 9. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090
51-85090 *F

CY7C1049D-10VXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4Mb 10ns 512K x 8 Fast Async SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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