DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
10 ____________________________________________________________________
date, month, and year information. The date at the end
of the month is automatically adjusted for months with
fewer than 31 days, including corrections for leap year.
The clock operates in either the 24-hour or 12-hour for-
mat with AM/PM indicator. Access to the internal regis-
ters is possible through an SPI bus interface.
A temperature-compensated voltage reference and
comparator circuit monitors the level of V
CC
to detect
power failures and to automatically switch to the backup
supply when necessary. When operating from the back-
up supply, access is inhibited to minimize supply cur-
rent. Oscillator, time and date, and TCXO operations can
continue while the backup supply powers the device.
The RST pin provides an external pushbutton function
and acts as an indicator of a power-fail event.
Operation
The block diagram shows the main elements of the
DS3234. The eight blocks can be grouped into four
functional groups: TCXO, power control, pushbutton
function, and RTC. Their operations are described sep-
arately in the following sections.
32kHz TCXO
The temperature sensor, oscillator, and control logic
form the TCXO. The controller reads the output of the
on-chip temperature sensor and uses a lookup table to
determine the capacitance required, adds the aging
correction in the AGE register, and then sets the
capacitance selection registers. New values, including
changes to the AGE register, are loaded only when a
change in the temperature value occurs. The tempera-
ture is read on initial application of V
CC
and once every
64 seconds (default, see the description for CRATE1
and CRATE0 in the
Control/Status Register
section)
afterwards.
Power Control
The power control function is provided by a tempera-
ture-compensated voltage reference and a comparator
circuit that monitors the V
CC
level. The device is fully
accessible and data can be written and read when V
CC
is greater than V
PF
. However, when V
CC
falls below
both V
PF
and V
BAT
, the internal clock registers are
blocked from any access. If V
PF
is less than V
BAT
, the
device power is switched from V
CC
to V
BAT
when V
CC
drops below V
PF
. If V
PF
is greater than V
BAT
, the
device power is switched from V
CC
to V
BAT
when V
CC
drops below V
BAT
. After V
CC
returns above both V
PF
and V
BAT
, read and write access is allowed after RST
goes high (Table 1).
To preserve the battery, the first time V
BAT
is applied to
the device, the oscillator does not start up until V
CC
crosses V
PF
. After the first time V
CC
is ramped up, the
oscillator starts up and the V
BAT
source powers the
oscillator during power-down and keeps the oscillator
running. When the DS3234 switches to V
BAT
, the oscil-
lator may be disabled by setting the EOSC bit.
V
BAT
Operation
There are several modes of operation that affect the
amount of V
BAT
current that is drawn. When the part is
powered by V
BAT
, timekeeping current (I
BATT
), which
includes the averaged temperature conversion current,
I
BATTC
, is drawn (refer to Application Note 3644:
Power
Considerations for Accurate Real-Time Clocks
for
details). Temperature conversion current, I
BATTC
, is
specified since the system must be able to support the
periodic higher current pulse and still maintain a valid
voltage level. Data retention current, I
BATTDR
, is the
current drawn by the part when the oscillator is
stopped (EOSC = 1). This mode can be used to mini-
mize battery requirements for times when maintaining
time and date information is not necessary, e.g., while
the end system is waiting to be shipped to a customer.
Pushbutton Reset Function
The DS3234 provides for a pushbutton switch to be
connected to the RST output pin. When the DS3234 is
not in a reset cycle, it continuously monitors the RST
signal for a low going edge. If an edge transition is
detected, the DS3234 debounces the switch by pulling
the RST low. After the internal timer has expired
(PB
DB
), the DS3234 continues to monitor the RST line.
If the line is still low, the DS3234 continuously monitors
the line looking for a rising edge. Upon detecting
release, the DS3234 forces the RST pin low and holds it
low for t
RST
.
The same pin, RST, is used to indicate a power-fail
condition. When V
CC
is lower than V
PF
, an internal
power-fail signal is generated, which forces the RST pin
low. When V
CC
returns to a level above V
PF
, the RST
pin is held low for t
REC
to allow the power supply to sta-
bilize. If the EOSC bit is set to logic 1 (to disable the
oscillator in battery-backup mode), t
REC
is bypassed
and RST immediately goes high.
SUPPLY CONDITION
READ/WRITE
ACCESS
ACTIVE
SUPPLY
RST
V
CC
< V
PF
, V
CC
< V
BAT
No V
BAT
Active
V
CC
< V
PF
, V
CC
> V
BAT
Yes V
CC
Active
V
CC
> V
PF
, V
CC
< V
BAT
Yes V
CC
Inactive
V
CC
> V
PF
, V
CC
> V
BAT
Yes V
CC
Inactive
Table 1. Power Control
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
____________________________________________________________________ 11
When RST is active due to a power-fail condition (see
Table 1), SPI operations are inhibited while the TCXO
and RTC continue to operate. When RST is active due
to a pushbutton event, it does not affect the operation
of the TCXO, SPI interface, or RTC functions.
Real-Time Clock
With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is auto-
matically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates
in either the 24-hour or 12-hour format with an AM/PM
indicator.
The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW pin either generates an interrupt due to alarm
condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.
SRAM
The DS3234 provides 256 bytes of general-purpose
battery-backed read/write memory. The SRAM can be
written or read whenever V
CC
is above either V
PF
or
V
BAT
.
Address Map
Figure 1 shows the address map for the DS3234 time-
keeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
(13h read, 93h write), it wraps around to the beginning
(00h read, 80h write). The DS3234 does not respond to
a read or write to any reserved address, and the inter-
nal address pointer does not increment. Address point-
er operation when accessing the 256-byte SRAM data
is covered in the description of the SRAM address and
data registers. On the falling edge of CS, or during a
multibyte access when the address pointer increments
to location 00h, the current time is transferred to a sec-
ond set of registers. The time information is read from
these secondary registers, while the internal clock reg-
isters continue to increment normally. If the time and
date registers are read using a multibyte read, this
eliminates the need to reread the registers in case the
main registers update during a read.
SPI Interface
The DS3234 operates as a slave device on the SPI seri-
al bus. Access is obtained by selecting the part by the
CS pin and clocking data into/out of the part using the
SCLK and DIN/DOUT pins. Multiple byte transfers are
supported within one CS low period. The SPI on the
DS3234 interface is accessible whenever V
CC
is above
either V
BAT
or V
PF
.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in
binary-coded decimal (BCD) format. The DS3234 can
be run in either 12-hour or 24-hour mode. Bit 6 of the
hours register is defined as the 12- or 24-hour mode
select bit. When high, 12-hour mode is selected. In 12-
hour mode, bit 5 is the AM/PM bit with logic-high being
PM. In 24-hour mode, bit 5 is the 20-hour bit (20–23
hours). The century bit (bit 7 of the month register) is
toggled when the years register overflows from 99 to
00.
The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the
time and date registers, the user buffers are synchro-
nized to the internal registers on the falling edge of CS
or and when the register pointer rolls over to zero. The
time information is read from these secondary registers,
while the clock continues to run. This eliminates the
need to reread the registers in case the main registers
update during a read.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur when the last
bit of a byte is clocked in. Once the countdown chain is
reset, to avoid rollover issues the remaining time and
date registers must be written within 1 second. The 1Hz
square-wave output, if enabled, transitions high 500ms
after the seconds data transfer.
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
12 ____________________________________________________________________
Figure 1. Address Map for DS3234 Timekeeping Registers and SRAM
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied. Bits defined as 0 cannot be written
to 1 and will always read 0.
ADDRESS
READ/WRITE
MSB
BIT 7
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
LSB
BIT 0
FUNCTION RANGE
00h 80h 0 10 Seconds Seconds Seconds 00–59
01h 81h 0 10 Minutes Minutes Minutes 00–59
AM/PM
02h 82h 0 12/24
20 hr
10 hr Hour Hours
1-12 +AM /PM
00-23
03h 83h 0 0 0 0 0 Day Day 1-7
04h 84h 0 0 10 Date Date Date 01-31
05h 85h Century 0 0 10 Mo Month
Month/
Century
01-12 + Century
06h 86h 10 Year Year Year 00-99
07h 87h A1M1 10 Seconds Seconds
Alarm 1
Seconds
00-59
08h 88h A1M2 10 Minutes Minutes
Alarm 1
Minutes
00-59
AM/PM
09h 89h A1M3 12/24
20 hr
10 hr Hour
Alarm 1
Hours
1-12 +AM /PM
00-23
0Ah 8Ah A1M4 DY/DT
0
10 Date
Day
Date
Alarm 1 Day
Alarm 1 Date
1-7
01-31
0Bh 8Bh A2M2 10 Minutes Minutes
Alarm 2
Minutes
00-59
AM/PM
0Ch 8Ch A2M3 12/24
20 hr
10 hr Hour
Alarm 2
Hours
1-12 +AM /PM
00-23
0Dh 8Dh A2M4 DY/DT
0
10 Date
Day
Date
Alarm 2 Day
Alarm 2 Date
1-7
01-31
0Eh 8Eh EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE Control
0Fh 8Fh OSF BB32kHz CRATE1 CRATE0 EN32kHz BSY A2F A1F
Control/
Status
10h 90h SIGN DATA DATA DATA DATA DATA DATA DATA
Crystal Aging
Offset
11h 91h SIGN DATA DATA DATA DATA DATA DATA DATA Temp MSB Read Only
12h 92h DATA DATA 0 0 0 0 0 0 Temp LSB Read Only
13h 93h 0 0 0 0 0 0 0 BB_TD
Disable
Temp
Conversions
14h–17h 94h–97h Reserved
18h 98h A7 A6 A5 A4 A3 A2 A1 A0
SRAM
Address
19h 99h D7 D6 D5 D4 D3 D2 D1 D0 SRAM Data

DS3234S#

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Real Time Clock Integrated RTC/TCXO/Crystal
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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