9DB1933AKLF Datasheet 9DB1933AKLF, 9DB1933AKLFT | P1-P3

9DB1933

IDT

Nineteen Output Differential Buffer for PCIe Gen3 1676A—07/12/10

Nineteen Output Differential Buffer for PCIe Gen3

DATASHEET

General Description

Output Features

The 9DB1933 zero-delay buffer supports PCIe Gen3

requirements, while being backwards compatible to PCIe Gen2

and Gen1. The 9DB1933 is driven by a differential SRC output

pair from an IDT 932S421, 932SQ420, or equivalent, main

clock generator. It attenuates jitter on the input clock and has a

selectable PLL bandwidth to maximize performance in systems

with or without Spread-Spectrum clocking.

• 19 - 0.7V current mode differential HCSL output pairs

Functional Block Diagram

Key Specifications

• Cycle-to-cycle jitter <50ps

• Output-to-output skew < 150 ps

• PCIe Gen3 phase jitter < 1.0ps RMS

Features/Benefits

• 8 Selectable SMBus Addresses/Mulitple devices can share

the same SMBus Segment

• 11 dedicated and 3 group OE# pins/Hardware control of the

outputs

• PLL or bypass mode/PLL can dejitter incoming clock

• Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL's

• Spread Spectrum Compatible/tracks spreading input clock

for low EMI

• SMBus Interface/unused outputs can be disabled

• Supports undriven differential outputs in Power Down mode

for power management

Recommended Application

19 output PCIe Gen3 zero-delay/fanout buffer

DIF_IN

DIF_IN#

DIF(18:0)

HIGH_BW#

SMB_A2_PLLBYP#

SMBDAT

SMBCLK

CKPWRGD/PD#

IREF

OE(17_18)#

OE(15_16)#

OE(14:5)#,

OE_01234#

SMB_A0

SMB_A1

PLL

(SS Compatible)

Logic

IDT

Nineteen Output Differential Buffer for PCIe Gen3

9DB1933

Nineteen Output Differential Buffer for PCIe Gen3

1676A—07/12/10

Pin Configuration

SMB_A2_PLLBYP#

DIF_IN#

DIF_IN

OE_17_18#

DIF_18#

DIF_18

DIF_17#

DIF_17

GND

VDD

DIF_16#

DIF_ 16

OE_15_16#

DIF_15#

DIF_15

CKPWRGD/PD#

DIF_14#

DIF_14

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

IREF 1 54 OE14#

GNDA 2 53 DIF_13#

VDDA 3 52 DIF_13

HIGH_BW# 4 51 OE13#

VDD 5 50 DIF_12#

DIF_0 6 49 DIF_12

DIF_0# 7 48 OE12#

DIF_1 8 47 VDD

DIF_1# 9 46 GND

GND 10 45 DIF_11#

VDD 11 44 DIF_11

DIF_2 12 43 OE11#

DIF_2# 13 42 DIF_10#

DIF_3 14 41 DIF_10

DIF_3# 15 40 OE10#

DIF_4 16 39 DIF_9#

DIF_4# 17 38 DIF_9

OE_01234# 18 37 OE9#

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

SMBCLK

SMBDAT

OE5#

DIF_5

DIF_5#

OE6#

DIF_6

DIF_6#

VDD

GND

OE7#

DIF_7

DIF_7#

OE8#

DIF_8

DIF_8#

SMB_A0

SMB_A1

9DB1933AKLF

VDD GND

3 2 PLL, Analog

5,11,27,47,63 10,28,46,64 DIF clocks

Description

Pin Number

Power Groups

Power Down Functionality

OUTPUTS

CKPWRGD/

PD#

DIF_IN/

DIF_IN#

DIF/DIF#

1 Running Running ON

0 X Hi-Z OFF

PLL State

INPUTS

IDT

Nineteen Output Differential Buffer for PCIe Gen3

9DB1933

Nineteen Output Differential Buffer for PCIe Gen3

1676A—07/12/10

Pin Description

PIN # PIN NAME PIN TYPE DESCRIPTION

1 IREF OUT

This pin establishes the reference current for the differential current-mode

output pairs. This pin requires a fixed precision resistor tied to ground in order

to establish the appropriate current. 475 ohms is the standard value.

2 GNDA PWR Ground pin for the PLL core.

VDDA

PWR

3.3V power for the PLL core.

4 HIGH_BW# IN

3.3V input for selecting PLL Band Width

0 = High, 1= Low

5 VDD PWR Power supply, nominal 3.3V

DIF_0

OUT

0.7V differential true clock output

7 DIF_0# OUT 0.7V differential Complementary clock output

8 DIF_1 OUT 0.7V differential true clock output

9 DIF_1# OUT 0.7V differential Complementary clock output

GND

PWR

Ground pin.

11 VDD PWR Power supply, nominal 3.3V

12 DIF_2 OUT 0.7V differential true clock output

13 DIF_2# OUT 0.7V differential Complementary clock output

14 DIF_3 OUT 0.7V differential true clock output

DIF_3#

OUT

0.7V differential Complementary clock output

16 DIF_4 OUT 0.7V differential true clock output

17 DIF_4# OUT 0.7V differential Complementary clock output

18 OE_01234# IN

Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.

1 =disable outputs, 0 = enable outputs

19 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant

20 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant

21 OE5# IN

Active low input for enabling DIF pair 5.

1 =disable outputs, 0 = enable outputs

22 DIF_5 OUT 0.7V differential true clock output

23 DIF_5# OUT 0.7V differential Complementary clock output

24 OE6# IN

Active low input for enabling DIF pair 6.

1 =disable outputs, 0 = enable outputs

DIF_6

OUT

0.7V differential true clock output

26 DIF_6# OUT 0.7V differential Complementary clock output

27 VDD PWR Power supply, nominal 3.3V

28 GND PWR Ground pin.

29 OE7# IN

Active low input for enabling DIF pair 7.

1 =disable outputs, 0 = enable outputs

30 DIF_7 OUT 0.7V differential true clock output

31 DIF_7# OUT 0.7V differential Complementary clock output

32 OE8# IN

Active low input for enabling DIF pair 8.

1 =disable outputs, 0 = enable outputs

33 DIF_8 OUT 0.7V differential true clock output

34 DIF_8# OUT 0.7V differential Complementary clock output

SMB_A0

SMBus address bit 0 (LSB)

36 SMB_A1 IN SMBus address bit 1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

9DB1933AKLF

Mfr. #:

Buy 9DB1933AKLF

Manufacturer:

IDT

Description:

Clock Buffer 19 OUTPUT PCIE GEN3 BUFFER

Lifecycle:

New from this manufacturer.

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9DB1933AKLF

9DB1933AKLF

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