9DB1933AKLF Datasheet 9DB1933AKLF, 9DB1933AKLFT | P13-P15

IDT

®

Nineteen Output Differential Buffer for PCIe Gen3

9DB1933

Nineteen Output Differential Buffer for PCIe Gen3

13

1676A—07/12/10

SMBusTable: Reserved Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

R

1

Bit 6

R

1

Bit 5

R

1

Bit 4

R

1

Bit 3

R

1

Bit 2

R

0

Bit 1

R

1

Bit 0 R

1

SMBusTable: Output Control Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

DIF_7 Output Control RW Hi-Z Enable 1

Bit 6

DIF_6

Output Control

RW

Hi-Z

Enable

1

Bit 5

DIF_5 Output Control RW Hi-Z Enable 1

Bit 4

DIF_4 Output Control RW Hi-Z Enable 1

Bit 3

DIF_3

Output Control

RW

Hi-Z

Enable

1

Bit 2

DIF_2 Output Control RW Hi-Z Enable 1

Bit 1

DIF_1

Output Control

RW

Hi-Z

Enable

1

Bit 0

DIF_0 Output Control RW Hi-Z Enable 1

SMBusTable: Output and PLL BW Control Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

RW High BW Low BW

1

Bit 6

RW Bypass PLL

1

Bit 5

DIF_13

Output Control

RW

Hi-Z

Enable

1

Bit 4

DIF_12 Output Control RW Hi-Z Enable 1

Bit 3

DIF_11 Output Control RW Hi-Z Enable 1

Bit 2

DIF_10

Output Control

RW

Hi-Z

Enable

1

Bit 1

DIF_9 Output Control RW Hi-Z Enable 1

Bit 0

DIF_8 Output Control RW Hi-Z Enable 1

Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW

Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode

SMBusTable: Output Enable Readback Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

R X

Bit 6

R

X

Bit 5

R X

Bit 4

R X

Bit 3

R

X

Bit 2

R X

Bit 1

R X

Bit 0

R X

72

see note PLL_BW# adjust

see note BYPASS# test mode / PLL

Byte 3

8

Byte 1

-

Byte 0

-

Reserved

-

Reserved

Readback

Readback - OE9# Input

Readback - OE8# Input

Readback

Readback - OE7# Input

ReadbackReadback - OE_01234# Input

Readback

Readback - OE5# Input

Readback - OE6# Input

Readback

Byte 2

Reserved

Readback - SMB_A2_PLLBYP# In

Readback

Readback - HIGH_BW# In Readback

Reserved

IDT

®

Nineteen Output Differential Buffer for PCIe Gen3

9DB1933

Nineteen Output Differential Buffer for PCIe Gen3

14

1676A—07/12/10

SMBusTable: Output Enable Readback Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

R

X

Bit 6

R X

Bit 5

0

Bit 4

R

X

Bit 3

R X

Bit 2

R

X

Bit 1

R

X

Bit 0

R X

SMBusTable: Vendor & Revision ID Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

RID3 R - - 0

Bit 6

RID2

R

-

0

Bit 5

RID1 R - - 0

Bit 4

RID0 R - - 1

Bit 3

VID3

R

-

0

Bit 2

VID2 R - - 0

Bit 1

VID1 R - - 0

Bit 0

VID0 R - - 1

SMBusTable: DEVICE ID (194 Decimal or C2 Hex)

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

RW

1

Bit 6

RW 1

Bit 5

RW 0

Bit 4

RW

0

Bit 3

RW 0

Bit 2

RW

0

Bit 1

RW

1

Bit 0

RW 0

SMBusTable: Byte Count Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

BC7 RW - - 0

Bit 6

BC6

RW

-

0

Bit 5

BC5 RW - - 0

Bit 4

BC4 RW - - 0

Bit 3

BC3

RW

-

0

Bit 2

BC2 RW - - 1

Bit 1

BC1 RW - - 1

Bit 0

BC0 RW - - 1

-

54

51

48

43

-

Reserved

Readback

Reserved

Readback

Reserved

Device ID 1

Reserved

Writing to this register

configures how many

bytes will be read back.

-

60

-

40

-

Readback - OE12# Input

VENDOR ID

Readback - OE11# Input

Device ID 5

Device ID 6

Device ID 7 (MSB)

REVISION ID

-

Byte 5

-

Byte 6

69

-

Reserved

Device ID 2

Byte 4

Readback - OE13# Input

Byte 7

-

Device ID 3

Device ID 4

Readback

Readback - OE10# Input

Readback - OE14# Input

Readback

ReservedDevice ID 0

Readback - OE15_16# Input

Readback - OE17_18# Input

IDT

®

Nineteen Output Differential Buffer for PCIe Gen3

9DB1933

Nineteen Output Differential Buffer for PCIe Gen3

15

1676A—07/12/10

SMBusTable: Output Control Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

1

Bit 6

X

Bit 5

X

Bit 4

DIF_18

Output Control

RW

Hi-Z

Enable

1

Bit 3

DIF_17 Output Control RW Hi-Z Enable 1

Bit 2

DIF_16

Output Control

RW

Hi-Z

Enable

1

Bit 1

DIF_15

Output Control

RW

Hi-Z

Enable

1

Bit 0

DIF_14 Output Control RW Hi-Z Enable 1

SMBusTable: Reserved Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

1

Bit 1

0

Bit 0

1

RESERVED

Byte 8

RESERVED

Byte 9

RESERVED

SMBus Address Mapping

SMBus Address

(Hex)

Main

Clock

(CKxxx) 9DB233 9DB433 9DB633 9DB833 9DB1233 9DB1933

D0



D2

 

D4

   

D6

 

D8

  

DA

  

DC

   

DE



Note:



Indicates Bypass Mode. PLL is OFF.

9DB1933AKLF

9DB1933AKLF

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