70V3569S5BFI8 Datasheet 70V3569S4BFG, 70V3569S4DRG, 70V3569S6BC | P1-P3

OCTOBER 2014

DSC 4831/13

1



Functional Block Diagram

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆

High-speed clock to data access

– Commercial: 4.2/5/6ns (max.)

– Industrial: 5ns (max)

◆

Pipelined output mode

◆

Counter enable and reset features

◆

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)

– Fast 4.2ns clock to data out

– 1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

◆

LVTTL- compatible, single 3.3V (±150mV) power supply for

core

◆

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)

power supply for I/Os and control signals on each port

◆

Industrial temperature range (-40°C to +85°C) is

available for selected speeds

◆

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-ball fine-pitch Ball Grid Array, and 256-pin Ball

Grid Array

◆

Green parts availble, see ordering instructions

HIGH-SPEED 3.3V 16K x 36

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70V3569S

CNTRST

R

Counter/

Address

Reg.

A

13R

A

0R

Counter/

Address

Reg.

CNTEN

R

ADS

R

CNTEN

L

ADS

L

CNTRST

L

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

B

W

0

L

B

W

1

L

B

W

2

L

B

W

3

L

B

W

3

R

B

W

2

R

B

W

1

R

B

W

0

R

I/O

0L

- I/O

35L

A

13L

A

0L

I/O

0R

-I/O

35R

Din_L

ADDR_L

Din_R

ADDR_R

OE

R

OE

L

4831 tbl 01

B

E

3L

BE

2L

BE

1L

BE

0L

R/W

L

CE

0L

B

E

3R

BE

2R

BE

1R

BE

0R

R/W

R

CE

0R

CE

1R

CE

1L

16K x 36

MEMORY

ARRAY

CLK

R

CLK

L

,

6.42

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

2

Description:

The IDT70V3569 is a high-speed 16K x 36 bit synchronous Dual-Port

RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneous access of any address from both ports. Registers on control,

data, and address inputs provide minimal setup and hold times. The timing

latitude provided by this approach allows systems to be designed with very

short cycle times. With an input data register, the IDT70V3569 has been

optimized for applications having unidirectional or bidirectional data flow

in bursts. An automatic power down feature, controlled by CE0 and CE1,

permits the on-chip circuitry of each port to enter a very low standby power

mode.

The 70V3569 can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power

supply for the core of the device (V

DD) remains at 3.3V.

Pin Configuration

(1,2,3,4)

NOTES:

1. All V

DD pins must be connected to 3.3V power supply.

2. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V

IL (0V).

3. All V

SS pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

A17

V

SS

B17

I/O

15R

C17

V

SS

D17

I/O

14R

E16

V

SS

E17

I/O

13L

D16

I/O

14L

C16

I/O

15L

B16

I/O

16L

A16

I/O

17L

A15

OPT

L

B15

V

DDQR

C15

I/O

16R

D15

V

DDQL

E15

I/O

13R

E14

I/O

12L

D14

I/O

17R

D13

V

DD

C12

A

6L

C14

V

DD

B14

V

SS

A14

A

0L

A12

CNTEN

L

B12

A

5L

C11

R/W

L

D12

A

3L

D11

CNTRST

L

C10

V

SS

B11

ADS

L

A11

CLK

L

D8

BE

0L

C8

BE

3L

A9

BE

1L

D9

V

DD

C9

CE

1L

B9

CE

0L

D10

OE

L

C7

A

10L

B8

BE

2L

A8

A

8L

B13

A

1L

A13

A

4L

A10

V

DD

D7

A

7L

B7

A

9L

B6

A

13L

C6

NC

D6

A

11L

B5

NC

C5

NC

D5

NC

B4

V

SS

C4

V

DD

D4

I/O

20L

B3

I/O

18R

C3

V

DDQR

D3

I/O

21L

D2

V

SS

C2

I/O

19R

B2

V

SS

B1

I/O

20R

C1

V

DDQL

D1

I/O

22L

E1

I/O

23L

E2

I/O

22R

E3

V

DDQR

E4

I/O

21R

F1

V

DDQL

F2

I/O

23R

F3

I/O

24L

F4

V

SS

G1

I/O

26L

G2

V

SS

G3

I/O

25L

G4

I/O

24R

H1

V

DD

H2

I/O

26R

H3

V

DDQR

H4

I/O

25R

J1

V

DDQL

J2

V

DD

J3

V

SS

J4

V

SS

K1

I/O

28R

K2

V

SS

K3

I/O

27R

K4

V

SS

L1

I/O

29R

L2

I/O

28L

L3

V

DDQR

L4

I/O

27L

M1

V

DDQL

M2

I/O

29L

M3

I/O

30R

M4

V

SS

N1

I/O

31L

N2

V

SS

N3

I/O

31R

N4

I/O

30L

P1

I/O

32R

P2

I/O

32L

P3

V

DDQR

P4

I/O

35R

R1

V

SS

R2

I/O

33L

R3

I/O

34R

R4

NC

T1

I/O

33R

T2

I/O

34L

T3

V

DDQL

T4

V

SS

U1

V

SS

U2

I/O

35L

U3

V

DD

U4

NC

P5

NC

R5

NC

U6

A

11R

P12

CNTEN

R

P8

A

8R

U10

OE

R

P9

BE

1R

R8

BE

2R

T8

BE

3R

U9

V

DD

P10

V

DD

T11

R/W

R

U8

BE

0R

P11

CLK

R

R12

A

5R

T12

A

6R

U12

A

3R

P13

A

4R

P7

A

12R

R13

A

1R

T13

A

2R

U13

A

0R

R6

A

13R

T5

NC

U7

A

7R

U14

V

DD

T14

V

SS

R14

V

SS

P14

I/O

2L

P15

I/O

3L

R15

V

DDQL

T15

I/O

0R

U15

OPT

R

U16

I/O

0L

U17

I/O

1L

T16

V

SS

T17

I/O

2R

R17

V

DDQR

R16

I/O

1R

P17

I/O

4L

P16

V

SS

N17

I/O

5L

N16

I/O

4R

N15

V

DDQL

N14

I/O

3R

M17

V

DDQR

M16

I/O

5R

M15

I/O

6L

M14

V

SS

L17

I/O

8L

L16

V

SS

L15

I/O

7L

L14

I/O

6R

K17

V

SS

K16

I/O

8R

K15

V

DDQL

K14

I/O

7R

J17

V

DDQR

J16

V

SS

J15

V

DD

J14

V

SS

H17

I/O

10R

H16

V

SS

H15

IO

9R

H14

V

DD

G17

I/O

11R

G16

I/O

10L

G15

V

DDQL

G14

I/O

9L

F17

V

DDQR

F16

I/O

11L

F14

V

SS

70V3569BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

F15

I/O

12R

R9

CE

0R

R11

ADS

R

T6

NC

T9

CE

1R

B10

V

SS

C13

A

2L

P6

NC

R10

V

SS

R7

A

9R

T10

V

SS

T7

A

10R

U5

NC

4831 drw 02c

,

A7

A

12L

A5

NC

A4

NC

A3

V

SS

A2

IO

18L

A1

IO

19L

A6

NC

12/12/01

6.42

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

3

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:

1. All V

DD pins must be connected to 3.3V power supply.

2. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V

IL (0V).

3. All V

SS pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

70V3569BC

BC-256

(5)

256-Pin BGA

Top View

(6)

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

NC

A16

NC

A15

NC

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

V

DD

C12

A

6L

C14

OPT

L

B14

V

DD

A14

A

0L

A12

A

5L

B12

A

4L

C11

ADS

L

D12

V

DDQR

D11

V

DDQR

C10

CLK

L

B11

CNTRST

L

A11

CNTEN

L

D8

V

DDQR

C8

BE

1L

A9

CE

1L

D9

V

DDQL

C9

BE

0L

B9

CE

0L

D10

V

DDQL

C7

A

7L

B8

BE

3L

A8

BE

2L

B13

A

1L

A13

A

2L

A10

OE

L

D7

V

DDQR

B7

A

9L

A7

A

8L

B6

A

12L

C6

A

10L

D6

V

DDQL

A5

NC

B5

NC

C5

A

13L

D5

V

DDQL

A4

NC

B4

NC

C4

NC

D4

V

DD

A3

NC

B3

NC

C3

V

SS

D3

I/O

20L

D2

I/O

19R

C2

I/O

19L

B2

NC

A2

NC

A1

NC

B1

I/O

18L

C1

I/O

18R

D1

I/O

20R

E1

I/O

21R

E2

I/O

21L

E3

I/O

22L

E4

V

DDQL

F1

I/O

23L

F2

I/O

22R

F3

I/O

23R

F4

V

DDQL

G1

I/O

24R

G2

I/O

24L

G3

I/O

25L

G4

V

DDQR

H1

I/O

26L

H2

I/O

25R

H3

I/O

26R

H4

V

DDQR

J1

I/O

27L

J2

I/O

28R

J3

I/O

27R

J4

V

DDQL

K1

I/O

29R

K2

I/O

29L

K3

I/O

28L

K4

V

DDQL

L1

I/O

30L

L2

I/O

31R

L3

I/O

30R

L4

V

DDQR

M1

I/O

32R

M2

I/O

32L

M3

I/O

31L

M4

V

DDQR

N1

I/O

33L

N2

I/O

34R

N3

I/O

33R

N4

V

DD

P1

I/O

35R

P2

I/O

34L

P3

NC

P4

NC

R1

I/O

35L

R2

NC

R3

NC

R4

NC

T1

NC

T2

NC

T3

NC

T4

NC

P5

A

13R

R5

NC

P12

A

6R

P8

BE

1R

P9

BE

0R

R8

BE

3R

T8

BE

2R

P10

CLK

R

T11

CNTEN

R

P11

ADS

R

R12

A

4R

T12

A

5R

P13

A

3R

P7

A

7R

R13

A

1R

T13

A

2R

R6

A

12R

T5

NC

T14

A

0R

R14

OPT

R

P14

I/O

0L

P15

I/O

0R

R15

NC

T15

NC

T16

NC

R16

NC

P16

I/O

1L

N16

I/O

2R

N15

I/O

1R

N14

I/O

2L

M16

I/O

4L

M15

I/O

3L

M14

I/O

3R

L16

I/O

5R

L15

I/O

4R

L14

I/O

5L

K16

I/O

7L

K15

I/O

6L

K14

I/O

6R

J16

I/O

8L

J15

I/O

7R

J14

I/O

8R

H16

I/O

10R

H15

IO

9L

H14

I/O

9R

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R

F15

I/O

13R

R9

CE

0R

R11

CNTRST

R

T6

A

11R

T9

CE

1R

A6

A

11L

B10

R/W

L

C13

A

3L

P6

A

10R

R10

R/W

R

R7

A

9R

T10

OE

R

T7

A

8R

,

E5

V

DD

E6

V

DD

E7

V

SS

E8

V

SS

E9

V

SS

E10

V

SS

E11

V

DD

E12

V

DD

E13

V

DDQR

F5

V

DD

F6

V

SS

F8

V

SS

F9

V

SS

F10

V

SS

F12

V

DD

F13

V

DDQR

G5

V

SS

G6

V

SS

G7

V

SS

G8

V

SS

G9

V

SS

G10

V

SS

G11

V

SS

G12

V

SS

G13

V

DDQL

H5

V

SS

H6

V

SS

H7

V

SS

H8

V

SS

H9

V

SS

H10

V

SS

H11

V

SS

H12

V

SS

H13

V

DDQL

J5

V

SS

J6

V

SS

J7

V

SS

J8

V

SS

J9

V

SS

J10

V

SS

J11

V

SS

J12

V

SS

J13

V

DDQR

K5

V

SS

K6

V

SS

K7

V

SS

K8

V

SS

L5

V

DD

L6

V

SS

L7

V

SS

L8

V

SS

M5

V

DD

M6

V

DD

M7

V

SS

M8

V

SS

N5

V

DDQR

N6

V

DDQR

N7

V

DDQL

N8

V

DDQL

K9

V

SS

K10

V

SS

K11

V

SS

K12

V

SS

L9

V

SS

L10

V

SS

L11

V

SS

L12

V

DD

M9

V

SS

M10

V

SS

M11

V

DD

M12

V

DD

N9

V

DDQR

N10

V

DDQR

N11

V

DDQL

N12

V

DDQL

K13

V

DDQR

L13

V

DDQL

M13

V

DDQL

N13

V

DD

F7

V

SS

F11

V

SS

4831 drw 02d

,

12/12/01

70V3569S5BFI8

70V3569S5BFI8

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