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70V3569S5BFI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
13
ADDRESS
An
CLK
DATA
OUT
Qx - 1
(2)
Qx
Qn
Qn + 2
(2)
Qn + 3
ADS
CNTEN
t
CYC2
t
CH2
t
CL2
4831 drw 11
t
SA
t
HA
t
SAD
t
HAD
t
CD2
t
DC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
Qn + 1
R/
W
ADDRESS
An An +1 An + 2 An + 3
An + 4
An + 5
DATA
IN
Dn + 3Dn + 2
CE
0
CLK
4831 drw 10
DATA
OUT
Qn
Qn + 4
CE
1
BE
n
OE
t
CH2
t
CL2
t
CYC2
t
CKLZ
t
CD2
t
OHZ
t
CD2
t
SD
t
HD
READ WRITE READ
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
(3)
(1)
t
SW
t
HW
(4)
Timing Waveform of Pipelined Read with Address Counter Advance
(1)
NOTES:
1. CE
0, OE, BEn = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = V
IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains
constant for subsequent clocks.
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)
(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
14
ADDRESS
An
D
0
t
CH2
t
CL2
t
CYC2
Q
0
Q
1
0
CLK
DATA
IN
R/
W
CNTRST
4831 drw 13
INTERNAL
(3)
ADDRESS
ADS
CNTEN
t
SRST
t
HRST
t
SD
t
HD
t
SW
t
HW
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATA
OUT
t
SA
t
HA
1 An An + 1
(4)
(5)
(6)
Ax
t
SAD
t
HAD
t
SCN
t
HCN
Timing Waveform of Write with Address Counter Advance
(1)
Timing Waveform of Counter Reset
(2)
NOTES:
1. CE
0, BEn, and R/W = VIL; CE1 and CNTRST = VIH.
2.
CE
0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = V
IL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: A
DDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = V
IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
ADDRESS
An
CLK
DATA
IN
Dn
Dn + 1
Dn + 1 Dn + 2
ADS
CNTEN
t
CH2
t
CL2
t
CYC2
4831 drw 12
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
t
SCN
t
HCN
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
15
Functional Description
The IDT70V3569 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide minimal set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal, however, the self-timed internal write
pulse is independent of the LOW to HIGH transition of the clock signal.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3569s for depth expan-
sion configurations. Two cycles are required with CE
0 LOW and CE1
HIGH to re-activate the outputs.
4831 drw 14
IDT70V3569
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
15
CE
1
CE
0
V
DD
V
DD
IDT70V3569
IDT70V3569
IDT70V3569
Control Inputs
Control Inputs
Control Inputs
Control Inputs
BE,
R/W,
OE ,
CLK,
ADS ,
CNTRST,
CNTEN
Depth and Width Expansion
The IDT70V3569 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3569 can also be used in applications requiring expanded
width, as indicated in Figure 4. Through combining the control signals, the
devices can be grouped as necessary to accommodate applications
needing 72-bits or wider.
Figure 4. Depth and Width Expansion with IDT70V3569
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

70V3569S5BFI8

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Buy 70V3569S5BFI8
Manufacturer:
IDT
Description:
SRAM 16K X 36 SYNCH DPRAM
Lifecycle:
New from this manufacturer.
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