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70V3569S5BFI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)
(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of V
DDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
70V3569S4
Com'l Only
70V3569S5
Com'l
& Ind
70V3569S6
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
t
CYC2
Clock Cycle Time (Pipelined) 7.5
____
10
____
12
____
ns
t
CH2
Clock High Time (Pipelined) 3
____
4
____
5
____
ns
t
CL 2
Clock Low Time (Pipelined) 3
____
4
____
5
____
ns
t
R
Clock Rise Time
____
3
____
3
____
3ns
t
F
Clock Fall Time
____
3
____
3
____
3ns
t
SA
Address Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HA
Address Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SC
Chip Enable Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HC
Chip Enable Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SB
Byte Enable Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HB
Byte Enable Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SW
R/W Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HW
R/W Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SD
Input Data Setup Time 1.8
____
2.0
____
2.0
____
ns
t
HD
Input Data Hold Time 0.7
____
0.7
____
1.0
____
ns
t
SAD
ADS Setup Time
1.8
____
2.0
____
2.0
____
ns
t
HA D
ADS Hold Time
0.7
____
0.7
____
1.0
____
ns
t
SCN
CNT EN Setup Time
1.8
____
2.0
____
2.0
____
ns
t
HC N
CNT EN Hold Time
0.7
____
0.7
____
1.0
____
ns
t
SRST
CNTRST Setup Time
1.8
____
2.0
____
2.0
____
ns
t
HRST
CNTRST Hold Time
0.7
____
0.7
____
1.0
____
ns
t
OE
(1)
Output Enable to Data Valid
____
4
____
5
____
6ns
t
OL Z
Output Enable to Output Low-Z 0
____
0
____
0
____
ns
t
OHZ
Output Enable to Output High-Z 1 4 1 4.5 1 5 ns
t
CD2
Clock to Data Valid (Pipelined)
____
4.2
____
5
____
6ns
t
DC
Data Output Hold After Clock High 1
____
1
____
1
____
ns
t
CKHZ
Clock High to Output High-Z 1 3 1 4.5 1.5 6 ns
t
CKLZ
Clock High to Output Low-Z 1
____
1
____
1
____
ns
Port-to-Port Delay
t
CO
Clock-to-Clock Offset 6
____
8
____
10
____
ns
4831 tbl 11
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
11
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
4831 drw 07
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
t
SC
t
HC
t
CKHZ
t
CKLZ
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
An An + 1 An + 2 An + 3
t
CYC2
t
CH2
t
CL2
R/
W
ADDRESS
CE
0
CLK
CE
1
BE
(0-3)
(3)
DATA
OUT
OE
t
CD2
t
CKLZ
Qn Qn + 1 Qn + 2
t
OHZ
t
OLZ
t
OE
4831 drw 06
(1)
(1)
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
SC
t
HC
t
SB
t
HB
(4)
(1 Latency)
(5)
(5)
Timing Waveform of a Multi-Device Pipelined Read
(1,2)
Timing Waveform of Read Cycle for Pipelined Operation
(2)
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = V
IL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE
0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BE
n was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3569 for this waveform,
and are setup for depth expansion in this example. ADDRESS
(B1) = ADDRESS(B2) in this situation.
2. BE
n, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
12
CLK
L
R/W
L
ADDRESS
L
DATA
INL
CLK
R
R/W
R
ADDRESS
R
DATA
OUTR
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
4831 drw 08
t
DC
R/
W
ADDRESS
An An +1 An + 2 An + 2
An + 3 An + 4
DATA
IN
Dn + 2
CE
0
CLK
4831 drw 09
Qn
Qn + 3
DATA
OUT
CE
1
BE
n
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
READ NOP READ
t
SD
t
HD
(3)
(1)
t
SW
t
HW
WRITE
(4)
Timing Waveform of Left Port Write to Pipelined
Right Port Read
(1,2)
NOTES:
1. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = V
IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If t
CO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be t
CO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be t
CO + tCYC + tCD2).
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = V
IL)
(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

70V3569S5BFI8

Mfr. #:
Buy 70V3569S5BFI8
Manufacturer:
IDT
Description:
SRAM 16K X 36 SYNCH DPRAM
Lifecycle:
New from this manufacturer.
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