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70V3569S5BFI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
Pin Configuration
(1,2,3,4)
(con't.)
NOTES:
1. All V
DD pins must be connected to 3.3V power supply.
2. All V
DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to V
IL (0V).
3. All V
SS pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
1
0
0
1
0
1
1
0
2
1
0
3
1
0
4
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
2
0
8
2
0
7
2
0
6
2
0
5
2
0
4
2
0
3
2
0
2
2
0
1
2
0
0
1
9
9
1
9
8
1
9
7
1
9
6
1
9
5
1
9
4
1
9
3
1
9
2
1
9
1
1
9
0
1
8
9
1
8
8
1
8
7
1
8
6
1
8
5
1
8
4
1
8
3
1
8
2
1
8
1
1
8
0
1
7
9
1
7
8
1
7
7
1
7
6
1
7
5
1
7
4
1
7
3
1
7
2
1
7
1
1
7
0
1
6
9
1
6
8
1
6
7
1
6
6
1
6
5
1
6
4
1
6
3
1
6
2
1
6
1
1
6
0
1
5
9
1
5
8
1
5
7
70V3569DR
DR-208
(5)
208-Pin PQFP
Top View
(6)
I/O
19L
I/O
19R
I/O
20L
I/O
20R
V
DDQL
V
SS
I/O
21L
I/O
21R
I/O
22L
I/O
22R
V
DDQR
V
SS
I/O
23L
I/O
23R
I/O
24L
I/O
24R
V
DDQL
V
SS
I/O
25L
I/O
25R
I/O
26L
I/O
26R
V
DDQR
V
SS
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SS
I/O
27R
I/O
27L
I/O
28R
I/O
28L
V
DDQR
V
SS
I/O
29R
I/O
29L
I/O
30R
I/O
30L
V
DDQL
V
SS
I/O
31R
I/O
31L
I/O
32R
I/O
32L
V
DDQR
V
SS
I/O
33R
I/O
33L
I/O
34R
I/O
34L
V
S
S
V
D
D
Q
L
I
/
O
3
5
R
I
/
O
3
5
L
V
D
D
V
S
S
N
C
N
C
N
C
N
C
N
C
N
C
N
C
N
C
A
1
3
R
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
B
E
3
R
B
E
2
R
B
E
1
R
B
E
0
R
C
E
1
R
C
E
0
R
V
D
D
V
D
D
V
S
S
V
S
S
C
L
K
R
O
E
R
R
/
W
R
A
D
S
R
C
N
T
E
N
R
C
N
T
R
S
T
R
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
V
D
D
V
S
S
V
S
S
O
P
T
R
I
/
O
0
L
I
/
O
0
R
V
D
D
Q
L
V
S
S
I/O
16L
I/O
16R
I/O
15L
I/O
15R
V
SS
V
DDQL
I/O
14L
I/O
14R
I/O
13L
I/O
13R
V
SS
V
DDQR
I/O
12L
I/O
12R
I/O
11L
I/O
11R
V
SS
V
DDQL
I/O
10L
I/O
10R
I/O
9L
I/O
9R
V
SS
V
DDQR
V
DD
V
DD
V
SS
V
SS
V
SS
V
DDQL
I/O
8R
I/O
8L
I/O
7R
I/O
7L
V
SS
V
DDQR
I/O
6R
I/O
6L
I/O
5R
I/O
5L
V
SS
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SS
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
V
S
S
V
D
D
Q
R
I
/
O
1
8
R
I
/
O
1
8
L
V
S
S
V
D
D
V
S
S
N
C
N
C
N
C
N
C
N
C
N
C
N
C
A
1
3
L
A
1
2
L
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
B
E
3
L
B
E
2
L
B
E
1
L
B
E
0
L
C
E
1
L
C
E
0
L
V
D
D
V
D
D
V
S
S
V
S
S
C
L
K
L
O
E
L
R
/
W
L
A
D
S
L
C
N
T
E
N
L
C
N
T
R
S
T
L
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
L
A
0
L
V
D
D
V
D
D
V
S
S
O
P
T
L
I
/
O
1
7
L
I
/
O
1
7
R
V
D
D
Q
R
V
S
S
4831 drw 02a
,
12/12/01
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
Pin Names
Left Port Right Port Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
13L
A
0R
- A
13R
Address
I/O
0L
- I/O
35L
I/O
0R
- I/O
35R
Data Input/Output
CLK
L
CLK
R
Clock
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
BE
0L
- BE
3L
BE
0R
- BE
3R
Byte Enables (9-bit bytes)
V
DDQ L
V
DDQR
Power (I/O Bus)
(3.3V or 2.5V)
(1 )
OPT
L
OPT
R
Option for selection V
DDQX
(1,2)
V
DD
Power
(3.3V)
(1 )
V
SS
Ground
(0V)
4831 tbl 01
OE
CLK
CE
0
CE
1
BE
3
BE
2
BE
1
BE
0
R/W
Byte 3
I/O
27-35
Byte 2
I/O
18-2 6
Byte 1
I/O
9-17
Byte 0
I/O
0-8
MODE
X
↑
HXXXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down
X
↑
XLXXXXXHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down
X
↑
LHHHHHXHigh-ZHigh-ZHigh-ZHigh-ZAll Bytes Deselected
X
↑
LHHHHLLHigh-ZHigh-ZHigh-Z D
IN
Write to Byte 0 Only
X
↑
LHHHLHLHigh-ZHigh-Z D
IN
High-Z Write to Byte 1 Only
X
↑
LHHLHHLHigh-Z D
IN
High-Z High-Z Write to Byte 2 Only
X
↑
LHLHHHL D
IN
High-Z High-Z High-Z Write to Byte 3 Only
X
↑
LHHHL LLHigh-ZHigh-Z D
IN
D
IN
Write to Lower 2 Bytes Only
X
↑
LHLLHHL D
IN
D
IN
High-Z High-Z Write to Upper 2 bytes Only
X
↑
LHLLLLL D
IN
D
IN
D
IN
D
IN
Write to All Bytes
L
↑
LHHHHLHHigh-ZHigh-ZHigh-Z D
OUT
Read Byte 0 Only
L
↑
LHHHLHHHigh-ZHigh-Z D
OUT
High-Z Read Byte 1 Only
L
↑
LHHLHHHHigh-Z D
OUT
High-Z High-Z Read Byte 2 Only
L
↑
LHLHHHH D
OUT
High-Z High-Z High-Z Read Byte 3 Only
L
↑
LHHHL LHHigh-ZHigh-Z D
OUT
D
OUT
Read Lower 2 Bytes Only
L
↑
LHLLHHHD
OUT
D
OUT
High-Z High-Z Read Upper 2 Bytes Only
L
↑
LHLLLLH D
OUT
D
OUT
D
OUT
D
OUT
Read All Bytes
H
↑
L H L L L L X High-Z High-Z High-Z High-Z Outputs Disabled
4831 tbl 02
NOTES:
1. V
DD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
6.42
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
6
Recommended Operating
Temperature and Supply Voltage
(1)
Recommended DC Operating
Conditions with V
DDQ at 2.5V
Absolute Maximum Ratings
(1)
Truth Table II—Address Counter Control
(1,2)
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE
0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE
0, CE1 and BEn
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to
< 20mA for the period of VTERM > VDD + 150mV.
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Address
Previous
Address
Addr
Used CLK
(6 )
ADS CNTEN CNTRST
I/O
(3 )
MODE
XX0
↑
XX L
(4)
D
I/ O
(0) Counter Reset to Address 0
An X An
↑
L
(4)
XHD
I/ O
(n) External Address Used
An Ap Ap
↑
HH H D
I/ O
(p) External Address Blocked—Counter disabled (Ap reused)
XApAp + 1
↑
H L
(5)
HD
I/O
(p+1) Counter Enabled—Internal Address generation
4831 tbl 03
Grade
Ambient
Temperature GND V
DD
Commercial 0
O
C to +70
O
C0V3.3V
+
150mV
Industrial -40
O
C to +85
O
C0V3.3V
+
150mV
4831 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 3.15 3.3 3.45 V
V
DDQ
I/O Supply Voltage
(3 )
2.375 2.5 2.625 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage
(3 )
(Address & Control Inputs)
1.7
____
V
DDQ
+ 125mV
(2 )
V
V
IH
Input High Voltage - I/O
(3)
1.7
____
V
DDQ
+ 125mV
(2 )
V
V
IL
Input Low Voltage -0.3
(1)
____
0.7 V
4831 tbl 05a
Symbol Rating Commercial
& Industrial
Unit
V
TE R M
(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6 V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output Current 50 mA
4831 tbl 06
NOTES:
1. V
IL > -1.5V for pulse width less than 10 ns.
2. V
TERM must not exceed VDDQ + 125mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
IL (0V), and VDDQX for that port must be
supplied as indicated above.
NOTES:
1. V
IL > -1.5V for pulse width less than 10 ns.
2. V
TERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to V
IH (3.3V), and VDDQX for that port must be
supplied as indicated above.
Recommended DC Operating
Conditions with V
DDQ at 3.3V
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 3.15 3.3 3.45 V
V
DDQ
I/O Supply Voltage
(3)
3.15 3.3 3.45 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage
(Address & Control Inputs)
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IH
Input High Voltage - I/O
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IL
Input Low Voltage -0.3
(1)
____
0.8 V
4831 tbl 05b
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

70V3569S5BFI8

Mfr. #:
Buy 70V3569S5BFI8
Manufacturer:
IDT
Description:
SRAM 16K X 36 SYNCH DPRAM
Lifecycle:
New from this manufacturer.
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