6.42
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
20 OCTOBER 16, 2008
Standard SRAM Interface Read/
Write Operation
The description of this section is applicable to either port when
configured to operate in Standard SRAM mode. Read/write operation with
standard SRAM interface configuration is the same as the ADM port except
addresses are presented on the address bus. Operation is controlled by
CS, OE and WE. A read operation is issued when WE is asserted HIGH.
A write operation is issued when WE is asserted LOW. The I/O bus is the
destination for read data and the source data for write data when the read
operation is issued. However, write data needs to be driven to the I/O when
the write operation is issued.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX) (1FFE for IDT70P259 and FFE for IDT70P249), where a write
is defined as the CS=WE=VIL per Truth Table III. The left port clears the
interrupt by accessing address location 3FFE when CS
R = OER = VIL, WE
is a "don't care". Likewise, the right port interrupt flag (INT
R) is asserted
when the left port writes to memory location 3FFF (HEX) (1FFF for
IDT70P259 and FFF for IDT70P249) and to clear the interrupt flag
(INT
R), the right port must read the memory location 3FFF. The message
(16 bits) at 3FFE or 3FFF is user-defined, since it is an addressable SRAM
location. If the interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table III for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the SRAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the SRAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation.
Functional Description
The IDT70P269/259/249 are low-power CMOS 16K/8K/4K x 16
dual-port static RAMs. The two ports support user configurable standard
SRAM or time-multiplexed address and data (ADM) interfaces. The two
ports provide separate control, address, and I/O pins that permit indepen-
dent, asynchronous read and write access to any memory location. The
IDT70P269/259/249 has an automatic power-down feature controlled by
CS. The CS controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CS HIGH).
Power Supply
The core voltage (VDD) can be 1.8V, 2.5V or 3.0V, as long as it is lower
than or equal to the I/O voltage. Each port can operate on independent
I/O voltages. This is determined by what is connected to the V
DDIOL and
V
DDIOR pins. The supported I/O standards are 1.8V/2.5V LVCMOS and
3.0V LVTTL.
The IDT70P269/259/249 includes power supply isolation functional-
ity which aids system power management. V
DD, VDDIOR and VDDIOL can all
be independently powered up/down which allows either port and/or the
core to be powered down when not in use. If VDDIOX is powered down,
but V
DD remains powered up all inputs to the core will be forced to
deasserted states at full swing DC values to minimize leakage current and
active power consumption. If VDD is powered down but VDDIOX remain
powered up, all outputs for the port(s) in question will remain in the state
they were in prior to power down.
ADM Interface Read/Write Operation
The description of this section is applicable to either port when
configured in ADM mode.
Three control signals, ADV, WE, and CS are used to perform the read/
write operation. Address signals are first applied to the I/O bus along with
CS LOW. The addresses are loaded from the I/O bus in response to the
rising edge of the Address Latch Enable (ADV) signal. It is necessary
to meet the set-up (tAVDS) and hold (tAVDH) times given in the AC
specifications with valid address information in order to properly latch the
addresses.
Once the address signals are latched in, a read operation is issued
when WE stays HIGH. The I/O bus becomes HIGH-Z once the address
signals meeting t
AVDH. The read data is driven on the I/O bus tOE after the
OE is asserted LOW, and held until t
HZOE or tHZCS after the rising edge of
OE or CS, whichever comes first.
A write operation is issued when WE is asserted LOW. The write
data is applied to the I/O bus right after address meets the hold time
(tAVDH). And write data is written with the rising edge of either WE or
CS, whichever comes first, and meets data set-up (t
SD) and hold (tHD)
times.
A write operation is issued when WE is asserted LOW. The write data
is applied to the I/O bus right after address meets the hold time (t
AVDH). And
write data is written with the rising edge of either WE or CS, whichever
comes first, and meets data set-up (tSD) and hold (tHD) times.
