6.42
9
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
OCTOBER 16, 2008
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1)
Symbol Parameter
70P269/259/249
Unit
65 ns 90 ns
Min. Max. Min. Max..
ADM Port Read Cycle
(2)
t
RC
Read Cycle Time 65
____
90
____
ns
t
ACC1
Random Access ADV Low to Data Valid
____
65
____
90 ns
t
ACC2
Random Access Address to Data Valid
____
65
____
90 ns
t
ACC3
Random Access CS to Data Valid
____
65
____
90 ns
t
AVDA
Random Access ADV High to Data Valid
____
35
____
50 ns
t
AVD
ADV Low Pulse
15
____
20
____
ns
t
AVDS
Address Set-up to ADV Rising Edge 15
____
20
____
ns
t
AVDH
Address Hold from ADV Rising Edge 3
____
5
____
ns
t
CSS
CS Set-up to ADV Rising Edge
7
____
10
____
ns
t
OE
OE Low to Data Valid
____
35
____
50 ns
t
LZOE
(3)
OE Low to I/O Low-Z
3
____
5
____
ns
t
HZOE
(3)
OE High to I/O High-Z
____
15
____
25 ns
t
HZCS
(3)
CS High to I/O High-Z
____
15
____
25 ns
t
DBE
UB/LB Low to I/O Valid
____
35
____
50 ns
t
LZBE
(3)
UB/LB Low to I/O Low-Z
3
____
5
____
ns
t
HZBE
(3)
UB/LB High to I/O High-Z
____
15
____
25 ns
t
AVOE
ADV High to OE Low
0
____
0
____
ns
t
PU
Chip Enable to Power Up Time 0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
____
65
____
90 ns
Standard Port Read Cycle
(4)
t
RC
Read Cycle Time 40
____
60
____
ns
t
AA
Address to Data Valid
____
40
____
60 ns
t
OHA
Output Hold from Address Change 5
____
5
____
ns
t
ACS
CS to Data Valid
____
40
____
60
ns
t
DOE
OE Low to Data Valid
____
25
____
35
ns
t
LZOE
(3)
OE Low to Data Low-Z
5
____
5
____
ns
t
HZOE
(3)
OE High to Data High-Z
____
10
____
30 ns
t
LZCS
(3)
CS Low to Data Low-Z
5
____
5
____
ns
t
HZCS
(3)
CS Low to Data High-Z
____
10
____
30 ns
t
LZBE
(3)
UB/LB Low to Data Low-Z
5
____
5
____
ns
t
HZBE
(3)
UB/LB High to Data High-Z
____
10
____
30 ns
t
ABE
UB/LB Access Time
____
40
____
60 ns
7146 tbl 12
NOTES:
1. VDD = 1.8V
2. ADM port timing applies to the left or right port when configured to ADM mode.
3. This parameter is guaranteed by design and is not tested.
4. Standard SRAM port timing applies to the left or right port when configured to standard SRAM mode.
