SC26C92C1A,512 Datasheet SC26C92C1A,518, SC26C92A1B,557, SC26C92C1B,551 | P10-P12

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

This feature may be used automatically “turnaround” a transceiver

when operating in a simplex system.

Transmitter Disable Note (W.R.T. Turnaround)

When the TxEMT bit is set the sequence of instructions: enable

transmitter — load transmit holding register — disable transmitter

will often result in nothing being sent. In the condition of the TxEMT

being set do not issue the disable until the TxRDY bit goes active

again after the character is loaded to the TxFIFO. The data is not

sent if the time between the end of loading the transmit holding

16x mode. One bit time in the 1x mode.

This is sometimes the condition when the RS485 automatic “turn-

around” is enabled . It will also occur when only one character is to

be sent and it is desired to disable the transmitter immediately after

the character is loaded.

In general, when it is desired to disable the transmitter before the

last character is sent AND the TxEMT bit is set in the status register

be sure the TxRDY bit is active immediately before issuing the

transmitter disable instruction. (TxEMT is always set if the transmit-

ter has underrun or has just been enabled), TxRDY sets at the end

of the “start bit” time. It is during the start bit that the data in the

transmit holding register is transferred to the transmit shift register.

Transmitter Flow control

The transmitter may be controlled by the CTSN input when enabled

by MR2(4). The CTSN input would be connected to RTSN output of

the receiver to which it is communicating. See further description in

the MR 1 and MR2 register descriptions.

Receiver

The SC26C92 is conditioned to receive data when enabled through

the command register. The receiver looks for a High-to-Low

(mark-to-space) transition of the start bit on the RxD input pin. If a

transition is detected, the state of the RxD pin is sampled each 16X

clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of

the bit time clock (1X clock mode). If RxD is sampled High, the start

bit is invalid and the search for a valid start bit begins again. If RxD

is still Low, a valid start bit is assumed and the receiver continues to

sample the input at one bit time intervals at the theoretical center of

the bit, until the proper number of data bits and parity bit (if any)

have been assembled, and one stop bit has been detected. The

least significant bit is received first. The data is then transferred to

the Receive FIFO and the RxRDY bit in the SR is set to a 1. This

condition can be programmed to generate an interrupt at OP4 or

OP5 and INTRN. If the character length is less than 8 bits, the most

significant unused bits in the RxFIFO are set to zero.

After the stop bit is detected, the receiver will immediately look for

the next start bit. However, if a non-zero character was received

without a stop bit (framing error) and RxD remains Low for one half

of the bit period after the stop bit was sampled, then the receiver

operates as if a new start bit transition had been detected at that

point (one-half bit time after the stop bit was sampled).

The parity error, framing error, and overrun error (if any) are strobed

into the SR at the received character boundary, before the RxRDY

status bit is set. If a break condition is detected (RxD is Low for the

entire character including the stop bit), a character consisting of all

zeros will be loaded into the RxFIFO and the received break bit in

the SR is set to 1. The RxD input must return to high for two (2)

clock edges of the X1 crystal clock for the receiver to recognize the

end of the break condition and begin the search for a start bit. This

will usually require a high time of one X1 clock period or 3 X1

edges since the clock of the controller is not synchronous to

the X1 clock.

Receiver FIFO

The RxFIFO consists of a First-In-First-Out (FIFO) stack with a

capacity of eight characters. Data is loaded from the receive shift

in the status register is set whenever one or more characters are

available to be read, and a FFULL status bit is set if all eight stack

positions are filled with data. Either of these bits can be selected to

cause an interrupt. A read of the RxFIFO outputs the data at the top

of the FIFO. After the read cycle, the data FIFO and its associated

status bits (see below) are ‘popped’ thus emptying a FIFO position

for new data.

Receiver Status Bits

There are five (5) status bits that are evaluated with each byte (or

character) received: received break, framing error, parity error, over-

run error, and change of break. The first three are appended to

each byte and stored in the RxFIFO. The last two are not necessar-

ily related to the byte being received or a byte that is in the RxFIFO.

They are however developed by the receiver state machine.

The received break, framing error, parity error and overrun error (if

any) are strobed into the RxFIFO at the received character bound-

ary, before the RxRDY status bit is set. For character mode (see

below) status reporting the SR (Status Register) indicates the condi-

tion of these bits for the character that is the next to be read from the

FIFO

The ”received break” will always be associated with a zero byte in

the RxFIFO. It means that zero character was a break character

and not a zero data byte. The reception of a break condition will

always set the ”change of break” (see below) status bit in the Inter-

rupt Status Register (ISR). The Change of break condition is reset

by a reset error status command in the command register

Break Detection

If a break condition is detected (RxD is Low for the entire character

including the stop bit), a character consisting of all zeros will be

loaded into the RxFIFO and the received break bit in the SR is set to

1. The change of break bit also sets in the ISR The RxD input must

return to high for two (2) clock edges of the X1 crystal clock for the

receiver to recognize the end of the break condition and begin the

search for a start bit.

This will usually require a high time of one X1 clock period or 3

X1 edges since the clock of the controller is not synchronous

to the X1 clock.

Framing Error

A framing error occurs when a non–zero character whose parity bit

(if used) and stop; bit are zero. If RxD remains low for one half of

the bit period after the stop bit was sampled, then the receiver

operates as if the start bit of the next character had been detected.

The parity error indicates that the receiver–generated parity was not

the same as that sent by the transmitter.

The framing, parity and received break status bits are reset when

the associated data byte is read from the RxFIFO since these “error”

conditions are attached to the byte that has the error

Overrun Error

The overrun error occurs when the RxFIFO is full, the receiver shift

receiver has 9 valid characters and the start bit of the 10

has been

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

seen. At this point the host has approximately 6/16–bit time to read

a byte from the RxFIFO or the overrun condition will be set. The

character then overruns the 9

and the 11

the 10

and so on

until an open position in the RxFIFO is seen. (“seen” meaning at

least one byte was read from the RxFIFO.)

Overrun is cleared by a use of the “error reset” command in the

command register.

The fundamental meaning of the overrun is that data has been lost.

Data in the RxFIFO remains valid. The receiver will begin placing

characters in the RxFIFO as soon as a position becomes vacant.

Note: Precaution must be taken when reading an overrun FIFO.

There will be 8 valid characters in the receiver FIFO. There will

be one character in the receiver shift register. However it will

NOT be known if more than one “over–running” character has

been received since the overrun bit was set. The 9

character

is received and read as valid but it will not be known how many

characters were lost between the two characters of the 8

and

reads of the RxFIFO

The ”Change of break” means that either a break has been detected

or that the break condition has been cleared. This bit is available in

the ISR. The break change bit being set in the ISR and the received

break bit being set in the SR will signal the beginning of a break. At

the termination of the break condition only the change of break in

the ISR will be set. After the break condition is detected the ter-

mination of the break will only be recognized when the RxD input

has returned to the high state for two successive edges of the 1x

clock; 1/2 to 1 bit time (see above).

The receiver is disabled by reset or via CR commands. A disabled

receiver will not interrupt the host CPU under any circumstance in

the normal mode of operation. If the receiver is in the multi–drop or

special mode, it will be partially enabled and thus may cause an

interrupt. Refer to section on Wake–Up and the register description

for MR1 for more information.

Receiver Status Modes (block and character)

In addition to the data word, three status bits (parity error, framing

error, and received break) are also appended to each data character

in the FIFO (overrun is not). Status can be provided in two ways, as

programmed by the error mode control bit in the mode register. In

the ‘character’ mode, status is provided on a character–by–charac-

ter basis; the status applies only to the character at the top of the

FIFO. In the ‘block’ mode, the status provided in the SR for these

three bits is the logical–OR of the status for all characters coming to

the top of the FIFO since the last ‘reset error’ command was issued.

In either mode reading the SR does not affect the FIFO. The FIFO

is ‘popped’ only when the RxFIFO is read. Therefore the status

Receiver Flow Control

The receiver can control the deactivation of RTS. If programmed to

operate in this mode, the RTSN output will be negated when a valid

start bit was received and the FIFO is full. When a FIFO position

becomes available, the RTSN output will be re–asserted automati-

cally. This feature can be used to prevent an overrun, in the receiv-

er, by connecting the RTSN output to the CTSN input of the

transmitting device.

Note: The transmitter may also control the “RTSN” pin. When

under transmitter control the meaning is completely changed.

The meaning is the transmission has ended. This signal is

usually used to switch (turnaround) a bi–directional driver from

transmit to receive.

If the receiver is disabled, the FIFO characters can be read. Howev-

er, no additional characters can be received until the receiver is

enabled again. If the receiver is reset, the FIFO and all of the re-

ceiver status, and the corresponding output ports and interrupt are

reset. No additional characters can be received until the receiver is

enabled again.

Receiver Reset and Disable

Receiver disable stops the receiver immediately – data being

assembled in the receiver shift register is lost. Data and status in

the FIFO is preserved and may be read. A re-enable of the receiver

after a disable will cause the receiver to begin assembling

characters at the next start bit detected. A receiver reset will discard

the present shift register date, reset the receiver ready bit (RxRDY),

clear the status of the byte at the top of the FIFO and re-align the

FIFO read/write pointers.

A ‘watchdog timer’ is associated with each receiver. Its interrupt is

enabled by MR0[7]. The purpose of this timer is to alert the control

processor that characters are in the RxFIFO which have not been

read and/or the data stream has stopped. This situation may occur

at the end of a transmission when the last few characters received

are not sufficient to cause an interrupt.

This counter times out after 64 bit times. It is reset each time a

character is transferred from the receiver shift register to the

RxFIFO or a read of the RxFIFO is executed.

Receiver Timeout Mode

In addition to the watch dog timer described in the receiver section,

the counter/timer may be used for a similar function. Its

programmability, of course, allows much greater precision of time

out intervals.

The timeout mode uses the received data stream to control the

counter. Each time a received character is transferred from the shift

is not received before the counter reaches zero count, the counter

ready bit is set, and an interrupt can be generated. This mode can

be used to indicate when data has been left in the RxFIFO for more

than the programmed time limit. Otherwise, if the receiver has been

programmed to interrupt the CPU when the receive FIFO is full, and

the message ends before the FIFO is full, the CPU may not know

there is data left in the FIFO. The CTU and CTL value would be

programmed for just over one character time, so that the CPU would

be interrupted as soon as it has stopped receiving continuous data.

This mode can also be used to indicate when the serial line has

been marking for longer than the programmed time limit. In this

case, the CPU has read all of the characters from the FIFO, but the

last character received has started the count. If there is no new

data during the programmed time interval, the counter ready bit will

get set, and an interrupt can be generated.

The timeout mode is enabled by writing the appropriate command to

the command register. Writing an ‘Ax’ to CRA or CRB will invoke

the timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will

disable the timeout mode. The timeout mode should only be used

by one channel at once, since it uses the C/T. If, however, the

timeout mode is enabled from both receivers, the timeout will occur

only when both receivers have stopped receiving data for the

timeout period. CTU and CTL must be loaded with a value greater

than the normal receive character period. The timeout mode

disables the regular START/STOP Counter commands and puts the

C/T into counter mode under the control of the received data stream.

Each time a received character is transferred from the shift register

to the RxFIFO, the C/T is stopped after 1 C/T clock, reloaded with

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

the value in CTU and CTL and then restarted on the next C/T clock.

If the C/T is allowed to end the count before a new character has

been received, the counter ready bit, ISR[3], will be set. If IMR[3] is

set, this will generate an interrupt. Receiving a character after the

C/T has timed out will clear the counter ready bit, ISR[3], and the

interrupt. Invoking the ‘Set Timeout Mode On’ command, CRx = ‘Ax’,

will also clear the counter ready bit and stop the counter until the

next character is received.

Time Out Mode Caution

When operating in the special time out mode, it is possible to

generate what appears to be a “false interrupt”, i.e., an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data stream.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

The CTS, RTS, CTS Enable Tx signals

CTS (Clear To Send) is usually meant to be a signal to the transmit-

ter meaning that it may transmit data to the receiver. The CTS input

is on pin IP0 or IP1 for the transmitter. The CTS signal is active low;

thus, it is called CTSN. RTS is usually meant to be a signal from the

receiver indicating that the receiver is ready to receive data. It is

also active low and is, thus, called RTSN. RTSN is on pin OP0 or

OP1. A receiver’s RTS output will usually be connected to the CTS

input of the associated transmitter. Therefore, one could say that

RTS and CTS are different ends of the same wire!

MR2(4) is the bit that allows the transmitter to be controlled by the

CTS pin ( IP0 or IP1). When this bit is set to one AND the CTS

input is driven high, the transmitter will stop sending data at the end

of the present character being serialized. It is usually the RTS out-

put of the receiver that will be connected to the transmitter’s CTS

input. The receiver will set RTS high when the receiver FIFO is full

AND the start bit of the ninth character is sensed. Transmission

then stops with nine valid characters in the receiver. When MR2(4)

is set to one, CTSN must be at zero for the transmitter to operate. If

MR2(4) is set to zero, the IP0 or IP1 pin will have no effect on the

operation of the transmitter.

MR1(7) is the bit that allows the receiver to control OP0 or OP1.

When OP0 or OP1 is controlled by the receiver, the meaning of that

pin will be RTS. However, a point of confusion arises in that these

pins may also be controlled by the transmitter. When the transmit-

ter is controlling them the meaning is not RTS at all. It is, rather, that

the transmitter has finished sending its last data byte.

Programming the OP0 or OP1 pin to be controlled by the receiver

and the transmitter at the same time is allowed, but would usually be

incompatible.

RTS can also be controlled by the commands 1000 and 1001 in the

command register. RTS is expressed at the OP0 or OP1 pin which

is still an output port. Therefore, the state of OP0 or OP1 should be

set low (either by commands of the CR register or by writing to the

SOPR or ROPR (Set or Reset Output Port Registers) for the receiv-

er to generate the proper RTS signal. The logic at the output is

basically a NAND of the bit in OPR(0) or OPR(1) register and the

RTS signal as generated by the receiver. When the RTS flow con-

trol is selected via the MR1(7) bit the state of the OPR(0) or OPR(1)

the MR registers) will return the OP pins pin to the control of the

OPR register.

Multidrop Mode (9-bit or Wake-Up)

The DUART is equipped with a wake up mode for multidrop

applications. This mode is selected by programming bits MR1A[4:3]

or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this

mode of operation, a ‘master’ station transmits an address character

followed by data characters for the addressed ‘slave’ station. The

slave stations, with receivers that are normally disabled, examine

the received data stream and ‘wakeup’ the CPU (by setting RxRDY)

only upon receipt of an address character. The CPU compares the

received address to its station address and enables the receiver if it

wishes to receive the subsequent data characters. Upon receipt of

another address character, the CPU may disable the receiver to

initiate the process again.

A transmitted character consists of a start bit, the programmed

number of data bits, and Address/Data (A/D) bit, and the

programmed number of stop bits. The polarity of the transmitted

A/D bit is selected by the CPU by programming bit

MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the

A/D bit position, which identifies the corresponding data bits as data

while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position,

which identifies the corresponding data bits as an address. The

CPU should program the mode register prior to loading the

corresponding data bits into the TxFIFO.

In this mode, the receiver continuously looks at the received data

stream, whether it is enabled or disabled. If disabled, it sets the

RxRDY status bit and loads the character into the RxFIFO if the

received A/D bit is a one (address tag), but discards the received

character if the received A/D bit is a zero (data tag). If enabled, all

received characters are transferred to the CPU via the RxFIFO. In

either case, the data bits are loaded into the data FIFO while the

A/D bit is loaded into the status FIFO position normally used for

parity error (SRA[5] or SRB[5]). Framing error, overrun error, and

break detect operate normally whether or not the receive is enabled.

PROGRAMMING

The operation of the DUART is programmed by writing control words

into the appropriate registers. Operational feedback is provided via

status registers which can be read by the CPU. The addressing of

the registers is described in Table 1.

The contents of certain control registers are initialized to zero on

RESET. Care should be exercised if the contents of a register are

changed during operation, since certain changes may cause

operational problems.

For example, changing the number of bits per character while the

transmitter is active may cause the transmission of an incorrect

character. In general, the contents of the MR, the CSR, and the

OPCR should only be changed while the receiver(s) and

transmitter(s) are not enabled, and certain changes to the ACR

should only be made while the C/T is stopped.

Each channel has 3 mode registers (MR0, 1, 2) which control the

basic configuration of the channel. Access to these registers is

controlled by independent MR address pointers. These pointers are

set to 0 or 1 by MR control commands in the command register

“Miscellaneous Commands”. Each time the MR registers are

accessed the MR pointer increments, stopping at MR2. It remains

pointing to MR2 until set to 0 or 1 via the miscellaneous commands

of the command register. The pointer is set to 1 on reset for

compatibility with previous Philips Semiconductors UART software.

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SC26C92C1A,512

Mfr. #:

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UART Interface IC UART DUAL W/FIFO

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SC26C92C1A,512

SC26C92C1A,512

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