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SC26C92C1A,512

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31
16
CTPU
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CTPU
0x06
C/T[15] C/T[14] C/T[13] C/T[12] C/T[11] C/T[10] C/T[9] C/T[8]
0x06
CTPL
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CTPL
0x07
C/T[7] C/T[6] C/T[5] C/T[4] C/T[3] C/T[2] C/T[1] C/T[0]
0x07
REGISTER DESCRIPTIONS Mode Registers
MR0 is accessed by setting the MR pointer to 0 via the command
register command B.
MR0A
MR0[7] – This bit controls the receiver watch dog timer. 0 = disable,
1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6] – Bit 2 of receiver FIFO interrupt level. This bit along with Bit
6 of MR1 sets the fill level of the 8 byte FIFO that generates the
receiver interrupt.
Table 3. Receiver FIFO Interrupt Fill Level
MR0[6] MR1[6] Interrupt Condition
0 0 1 or more bytes in FIFO
(Rx RDY)
0 1 3 or more bytes in FIFO
1 0 6 or more bytes in FIFO
1 1 8 bytes in FIFO
(Rx FULL)
For the receiver these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
MR0[5:4] – Tx interrupt fill level.
Table 4. Transmitter FIFO Interrupt Fill Level
MR0[5] MR0[4] Interrupt Condition
0 0 8 bytes empty
(Tx EMPTY)
0 1 4 or more bytes empty
1 0 6 or more bytes empty
1 1 1 or more bytes empty
(Tx RDY)
For the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is completely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
MR0[3] – Not used. Should be set to 0.
MR0[2:0] – These bits are used to select one of the six baud rates
(see Table 5).
000 Normal mode
001 Extended mode I
100 Extended mode II
Other combinations should not be used
Note: MR0[3:0] are not used in channel B and should be set to 0.
MR1A
MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CR command 1. After reading or writing MR1A, the
pointer will point to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Control
(Flow Control)
This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0].
MR1A[7] = 1 causes RTSAN to be negated (OP0 is driven to a ‘1’
[V
CC
]) upon receipt of a valid start bit if the Channel A FIFO is full.
This is the beginning of the reception of the ninth byte. If the FIFO is
not read before the start of the tenth byte, an overrun condition will
occur and the tenth byte will be lost. However, the bit in OPR[0] is
not reset and RTSAN will be asserted again when an empty FIFO
position is available. This feature can be used for flow control to
prevent overrun in the receiver by using the RTSAN output signal to
control the CTSN input of the transmitting device.
MR1[6] – Bit 1 of the receiver interrupt control. See description
under MR0[6].
MR1A[5] – Channel A Error Mode Select
This bit select the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
MR1A[4:3| – Channel A Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type Select
This bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it
selects the polarity of the A/D bit.
MR1A[1:0] – Channel A Bits Per Character Select
This field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31
17
MR2A – Channel A Mode Register 2
MR2A is accessed when the Channel A MR pointer points to MR2,
which occurs after any access to MR1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6] – Channel A Mode Select
Each channel of the DUART can operate in one of four modes.
MR2A[7:6] = 00 is the normal mode, with the transmitter and
receiver operating independently.
MR2A[7:6] = 01 places the channel in the automatic echo mode,
which automatically retransmits the received data. The following
conditions are true while in automatic echo mode:
1. Received data is reclocked and retransmitted on the TxDA out-
put.
2. The receive clock is used for the transmitter. Data is received on
the rising edge of the RxC1x clock and retransmitted on the next
fall of the RxC!x clock.
3. The receiver must be enabled, but the transmitter need not be
enabled.
4. The Channel A TxRDY and TxEMT status bits are inactive.
5. The received parity is checked, but is not regenerated for trans-
mission, i.e. transmitted parity bit is as received.
6. Character framing is checked, but the stop bits are retransmitted
as received.
7. A received break is echoed as received until the next valid start
bit is detected.
8. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
MR2A(7:6) = 10 selects the local loop back diagnostic mode. In this
mode:
1. The transmitter output is internally connected to the receiver
input.
2. The transmit clock is used for the receiver.
3. The TxDA output is held High.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but the receiver need not be
enabled.
6. CPU to transmitter and receiver communications continue nor-
mally.
MR2A[7:6] = 11 selects a remote loop back diagnostic mode. In this
mode:
1. Received data is reclocked and retransmitted on the TxDA out-
put.
2. The receive clock is used for the transmitter.
3. Received data is not sent to the local CPU, and the error status
conditions are inactive.
4. The received parity is not checked and is not regenerated for
transmission, i.e., transmitted parity is as received.
5. The receiver must be enabled.
6. Character framing is not checked, and the stop bits are retrans-
mitted as received.
7. A received break is echoed as received until the next valid start
bit is detected.
8. A delay of one bit time is seen at the remote receiver.
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes: if the
de-selection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop has been re-transmitted.
MR2A[5] – Channel A Transmitter Request-to-Send Control
This bit controls the deactivation of the RTSAN output (OP0) by the
transmitter. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0].
MR2A[5] = 1 caused OPR[0] to be reset automatically one bit time
after the characters in the Channel A transmit shift register and in
the TxFIFO, if any, are completely transmitted including the
programmed number of stop bits. If the transmitter is not enabled,
this feature can be used to automatically terminate the transmission
of a message as follows:
1. Program auto-reset mode: MR2A[5] = 1.
2. Enable transmitter.
3. Asset RTSAN: OPR[0] = 1.
4. Send message.
5. Disable transmitter after the last character is loaded into the
Channel A TxFIFO. Tx status and Tx interrupts will be disabled
at this time.
6. The last character will be transmitted and OPR[0] will be reset
one bit time after the last stop bit, causing RTSAN to be negated.
In this mode, the meaning of “RTSAN” is that the transmission is
ended.
MR2A[4] – Channel A Clear-to-Send Control
If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a
1, the transmitter checks the state of CTSAN (IPO) each time it is
ready to send a character. If IPO is asserted (Low), the character is
transmitted. If it is negated (High), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes
low. Changes in CTSAN while a character is being transmitted do
not affect the transmission of that character..
MR2A[3:0] – Channel A Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1-9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1-1/16
to 2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a ‘mark’ condition at the center
of the stop bit position (one–half bit time after the last data bit, or
after the parity bit if enabled is sampled).
If an external 1X clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted.
MR0B – Channel B Mode Register 0
MR0B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR0 by RESET or by a ‘set pointer’ command
Philips Semiconductors Product specification
SC26C92
Dual universal asynchronous receiver/transmitter (DUART)
2000 Jan 31
18
applied via CRB. After reading or writing MR0B, the pointer will
point to MR1B.
The bit definitions for this register are identical to MR0A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs. MR0B[3:0] are reserved.
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will
point to MR2B.
The bit definitions for this register are identical to MR1A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs.
MR2B – Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode register are identical to the bit
definitions for MR2A, except that all control actions apply to the
Channel B receiver and transmitter and the corresponding inputs
and outputs.
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A receiver.
The field definition is shown in Table 5.
CSRB[7:4]
ACR[7] = 0 ACR[7] = 1
1110
1111
IP4-16X
IP4-1X
IP4-16X
IP4-1X
The receiver clock is always a 16X clock except for CSRB[7:4] = 1111.
CSRA[3:0] – Channel A Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as shown in Table 5, except as follows:
CSRA[3:0]
ACR[7] = 0 ACR[7] = 1
1110
1111
IP3-16X
IP3-1X
IP3-16X
IP3-1X
The transmitter clock is always a 16X clock except for CSR[3:0] = 1111.
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock Select
This field selects the baud rate clock for the Channel B receiver.
The field definition is as shown in Table 5, except as follows:
CSRB[7:4]
ACR[7] = 0 ACR[7] = 1
1110
1111
IP6-16X
IP6-1X
IP6-16X
IP6-1X
The receiver clock is always a 16X clock except for CSRB[7:4] = 1111.
CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as shown in Table 5, except as follows:
CSRB[3:0]
ACR[7] = 0 ACR[7] = 1
1110
1111
IP5-16X
IP5-1X
IP5-16X
IP5-1X
The transmitter clock is always a 16X clock except for
CSRB[3:0] = 1111.
Table 5. Baud Rate (Base on a 3.6864MHz crystal clock)
MR0[0] = 0 (Normal Mode) MR0[0] = 1 (Extended Mode I) MR0[2] = 1 (Extended Mode II)
CSRA[7:4] ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1 ACR[7] = 0 ACR[7] = 1
0000 50 75 300 450 4,800 7,200
0001 110 110 110 110 880 880
0010 134.5 134.5 134.5 134.5 1,076 1,076
0011 200 150 1200 900 19.2K 14.4K
0100 300 300 1800 1800 28.8K 28.8K
0101 600 600 3600 3600 57.6K 57.6K
0110 1,200 1,200 7200 7,200 115.2K 115.2K
0111 1,050 2,000 1,050 2,000 1,050 2,000
1000 2,400 2,400 14.4K 14.4K 57.6K 57.6K
1001 4,800 4,800 28.8K 28.8K 4,800 4,800
1010 7,200 1,800 7,200 1,800 57.6K 14.4K
1011 9,600 9,600 57.6K 57.6K 9,600 9,600
1100 38.4K 19.2K 230.4K 115.2K 38.4K 19.2K
1101 Timer Timer Timer Timer Timer Timer
1110 IP4-16X IP4-16X IP4-16X IP4-16X IP4-16X IP4-16X
1111 IP4-1X IP4-1X IP4-1X IP4-1X IP4-1X IP4-1X
NOTE: The receiver clock is always a 16X clock except for CSRA[7:4] = 1111.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

SC26C92C1A,512

Mfr. #:
Buy SC26C92C1A,512
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC UART DUAL W/FIFO
Lifecycle:
New from this manufacturer.
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