SC26C92C1A,512 Datasheet SC26C92C1A,518, SC26C92A1B,557, SC26C92C1B,551 | P19-P21

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

CRA – Channel A Command Register

CRA is a register used to supply commands to Channel A. Multiple

commands can be specified in a single write to CRA as long as the

commands are non-conflicting, e.g., the ‘enable transmitter’ and

‘reset transmitter’ commands cannot be specified in a single

command word.

CRA[7:4] – Miscellaneous Commands

Execution of the commands in the upper four bits of this register

must be separated by 3 X1 clock edges. Other reads or writes

(including writes tot he lower four bits) may be inserted to achieve

this separation.

CRA[7:4] – Command

0000 No command.

0001 Reset MR pointer. Causes the Channel A MR pointer to point

to MR1.

0010 Reset receiver. Resets the Channel A receiver as if a

hardware reset had been applied. The receiver is disabled

and the FIFO is flushed.

0011 Reset transmitter. Resets the Channel A transmitter as if a

hardware reset had been applied.

0100 Reset error status. Clears the Channel A Received Break, Parity

Error, and Overrun Error bits in the status register (SRA[7:4]).

Used in character mode to clear OE status (although RB, PE

and FE bits will also be cleared) and in block mode to clear all

error status after a block of data has been received.

0101 Reset Channel A break change interrupt. Causes the

Channel A break detect change bit in the interrupt status

0110 Start break. Forces the TxDA output Low (spacing). If the

transmitter is empty the start of the break condition will be

delayed up to two bit times. If the transmitter is active the

break begins when transmission of the character is

completed. If a character is in the TxFIFO, the start of the

break will be delayed until that character, or any other loaded

subsequently are transmitted. The transmitter must be

enabled for this command to be accepted.

0111 Stop break. The TxDA line will go High (marking) within two

bit times. TxDA will remain High for one bit time before the

next character, if any, is transmitted.

1000 Assert RTSN. Causes the RTSN output to be asserted

(Low).

1001 Negate RTSN. Causes the RTSN output to be negated

(High).

1010 Set Timeout Mode On. The receiver in this channel will

restart the C/T as each receive character is transferred from

the shift register to the RxFIFO. The C/T is placed in the

counter mode, the START/STOP counter commands are

disabled, the counter is stopped, and the Counter Ready Bit,

ISR[3], is reset. (See also Watchdog timer description in the

receiver section.)

1011 Set MR pointer to ‘0’

1100 Disable Timeout Mode. This command returns control of the

C/T to the regular START/STOP counter commands. It does

not stop the counter, or clear any pending interrupts. After

disabling the timeout mode, a ‘Stop Counter’ command

should be issued to force a reset of the ISR(3) bit.

1101 Not used.

1110 Power Down Mode On. In this mode, the DUART oscillator is

stopped and all functions requiring this clock are suspended.

The execution of commands other than disable power down

mode (1111) requires a X1/CLK. While in the power down

mode, do not issue any commands to the CR except the

disable power down mode command. The contents of all

registers will be saved while in this mode. . It is

recommended that the transmitter and receiver be disabled

prior to placing the DUART into power down mode. This

command is in CRA only.

1111 Disable Power Down Mode. This command restarts the

oscillator. After invoking this command, wait for the oscillator

to start up before writing further commands to the CR. This

command is in CRA only. For maximum power reduction

input pins should be at V

or V

CRA[3] – Disable Channel A Transmitter

This command terminates transmitter operation and reset the

TxDRY and TxEMT status bits. However, if a character is being

transmitted or if a character is in the TxFIFO when the transmitter is

disabled, the transmission of the character(s) is completed before

assuming the inactive state.

CRA[2] – Enable Channel A Transmitter

Enables operation of the Channel A transmitter. The TxRDY and

TxEMT status bits will be asserted if the transmitter is idle.

CRA[1] – Disable Channel A Receiver

This command terminates operation of the receiver immediately – a

character being received will be lost. The command has no effect

on the receiver status bits or any other control registers. If the

special multidrop mode is programmed, the receiver operates even

if it is disabled. See Operation section.

CRA[0] – Enable Channel A Receiver

Enables operation of the Channel A receiver. If not in the special

wakeup mode, this also forces the receiver into the search for

start-bit state.

CRB – Channel B Command Register

CRB is a register used to supply commands to Channel B. Multiple

commands can be specified in a single write to CRB as long as the

commands are non-conflicting, e.g., the ‘enable transmitter’ and

‘reset transmitter’ commands cannot be specified in a single

command word.

The bit definitions for this register are identical to the bit definitions

for CRA, with the exception of commands “Ex” and “Fx” which are

used for power downmode. These two commands are not used in

CRB. All other control actions that apply to CRA also apply to CRB.

SRA – Channel A Status Register

SRA[7] – Channel A Received Break

This bit indicates that an all zero character of the programmed

length has been received without a stop bit. Only a single FIFO

position is occupied when a break is received: further entries to the

FIFO are inhibited until the RxDA line returns to the marking state

for at least one-half a bit time two successive edges of the internal

or external 1X clock. This will usually require a high time of one

X1 clock period or 3 X1 edges since the clock of the controller

is not synchronous to the X1 clock.

When this bit is set, the Channel A ‘change in break’ bit in the ISR

(ISR[2]) is set. ISR[2] is also set when the end of the break

condition, as defined above, is detected.

The break detect circuitry can detect breaks that originate in the

middle of a received character. However, if a break begins in the

middle of a character, it must persist until at least the end of the next

character time in order for it to be detected.

This bit is reset by command 4 (0100) written to the command

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

SRA[6] – Channel A Framing Error

This bit, when set, indicates that a stop bit was not detected (not a

logical 1) when the corresponding data character in the FIFO was

received. The stop bit check is made in the middle of the first stop

bit position.

SRA[5] – Channel A Parity Error

This bit is set when the ‘with parity’ or ‘force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity.

In the special multidrop mode the parity error bit stores the receive

A/D (Address/Data) bit.

SRA[4] – Channel A Overrun Error

This bit, when set, indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of a new

character when the FIFO is full and a character is already in the

receive shift register waiting for an empty FIFO position. When this

occurs, the character in the receive shift register (and its break

detect, parity error and framing error status, if any) is lost.

This bit is cleared by a ‘reset error status’ command.

SRA[3] – Channel A Transmitter Empty (TxEMTA)

This bit will be set when the transmitter underruns, i.e., both the

TxEMT and TxRDY bits are set. This bit and TxRDY are set when

the transmitter is first enabled and at any time it is re-enabled after

either (a) reset, or (b) the transmitter has assumed the disabled

state. It is always set after transmission of the last stop bit of a

character if no character is in the THR awaiting transmission.

It is reset when the THR is loaded by the CPU, a pending

transmitter disable is executed, the transmitter is reset, or the

transmitter is disabled while in the underrun condition.

SRA[2] – Channel A Transmitter Ready (TxRDYA)

This bit, when set, indicates that the transmit FIFO is not full and

ready to be loaded with another character. This bit is cleared when

the transmit FIFO is loaded by the CPU and there are (after this

load) no more empty locations in the FIFO. It is set when a

character is transferred to the transmit shift register. TxRDYA is

reset when the transmitter is disabled and is set when the

transmitter is first enabled. Characters loaded to the TxFIFO while

this bit is 0 will be lost. This bit has different meaning from ISR[0].

SRA[1] – Channel A FIFO Full (FFULLA)

This bit is set when a character is transferred from the receive shift

become full, i.e., all eight FIFO positions are occupied. It is reset

when the CPU reads the receive FIFO. If a character is waiting in

the receive shift register because the FIFO is full, FFULLA will not

be reset when the CPU reads the receive FIFO. This bit has

different meaning from ISR1 when MR1 6 is programmed to a ‘1’.

SRA[0] – Channel A Receiver Ready (RxRDYA)

This bit indicates that a character has been received and is waiting

in the FIFO to be read by the CPU. It is set when the character is

transferred from the receive shift register to the FIFO and reset

when the CPU reads the receive FIFO, only if (after this read) there

are no more characters in the FIFO. The RxFIFO becomes empty.

SRB – Channel B Status Register

The bit definitions for this register are identical to the bit definitions

for SRA, except that all status applies to the Channel B receiver and

transmitter and the corresponding inputs and outputs.

OPCR – Output Port Configuration Register

OPCR[7] – OP7 Output Select

This bit programs the OP7 output to provide one of the following:

0 The complement of OPR[7].

1 The Channel B transmitter interrupt output which is the comple-

ment of ISR[4]. When in this mode OP7 acts as an open- drain

output. Note that this output is not masked by the contents of the

IMR.

OPCR[6] – OP6 Output Select

This bit programs the OP6 output to provide one of the following:

0 The complement of OPR[6].

1 The Channel A transmitter interrupt output which is the comple-

ment of ISR[0]. When in this mode OP6 acts as an open- drain

output. Note that this output is not masked by the contents of the

IMR.

OPCR[5] – OP5 Output Select

This bit programs the OP5 output to provide one of the following:

0 The complement of OPR[5].

1 The Channel B receiver interrupt output which is the complement

of ISR[5]. When in this mode OP5 acts as an open-drain output.

Note that this output is not masked by the contents of the IMR.

OPCR[4] – OP4 Output Select

This field programs the OP4 output to provide one of the following:

0 The complement of OPR[4].

1 The Channel A receiver interrupt output which is the complement

of ISR[1]. When in this mode OP4 acts as an open-drain output.

Note that this output is not masked by the contents of the IMR.

OPCR[3:2] – OP3 Output Select

This bit programs the OP3 output to provide one of the following:

00 The complement of OPR[3].

01 The counter/timer output, in which case OP3 acts as an open-

drain output. In the timer mode, this output is a square wave at

the programmed frequency. In the counter mode, the output

remains High until terminal count is reached, at which time it

goes Low. The output returns to the High state when the counter

is stopped by a stop counter command. Note that this output is

not masked by the contents of the IMR.

10 The 1X clock for the Channel B transmitter, which is the clock

that shifts the transmitted data. If data is not being transmitted, a

free running 1X clock is output.

11 The 1X clock for the Channel B receiver, which is the clock that

samples the received data. If data is not being received, a free

running 1X clock is output.

OPCR[1:0] – OP2 Output Select

This field programs the OP2 output to provide one of the following:

00 The complement of OPR[2].

01 The 16X clock for the Channel A transmitter. This is the clock

selected by CSRA[3:0], and will be a 1X clock if CSRA[3:0] =

1111.

10 The 1X clock for the Channel A transmitter, which is the clock

that shifts the transmitted data. If data is not being transmitted, a

free running 1X clock is output.

11 The 1X clock for the Channel A receiver, which is the clock that

samples the received data. If data is not being received, a free

running 1X clock is output.

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

SOPR – Set the Output Port Bits (OPR)

SOPR[7:0] – Ones in the byte written to this register will cause the

corresponding bit positions in the OPR to set to 1. Zeros have no

effect.

ROPR – Reset Output Port Bits (OPR)

ROPR[7:0] – Ones in the byte written to the ROPR will cause the

corresponding bit positions in the OPR to set to 0. Zeros have no effect.

Table 6. Bit Rate Generator Characteristics

Crystal or Clock = 3.6864MHz

NORMAL RATE

(BAUD)

ACTUAL 16X

CLOCK (kHz)

ERROR (%)

50 0.8 0

75 1.2 0

110 1.759 -0.069

134.5 2.153 0.059

150 2.4 0

200 3.2 0

300 4.8 0

600 9.6 0

1050 16.756 -0.260

1200 19.2 0

1800 28.8 0

2000 32.056 0.175

2400 38.4 0

4800 76.8 0

7200 115.2 0

9600 153.6 0

14.4K 230.4 0

19.2K 307.2 0

28.8K 460.8 0

38.4K 614.4 0

57.6K 921.6 0

115.2K 1843.2K 0

230.4K 3686.4K 0

NOTE: Duty cycle of 16X clock is 50% ± 1%.

Asynchronous UART communications can tolerate frequency error

of 4.1% to 6.7% in a “clean” communications channel. The percent

of error changes as the character length changes. The above

percentages range from 5 bits not parity to 8 bits with parity and one

stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a

stop bit length of 9/16 is used, the error tolerance will approach 0

due to a variable error of up to 1/16 bit time in receiver clock phase

alignment to the start bit.

ACR – Auxiliary Control Register

ACR[7] – Baud Rate Generator Set Select

This bit selects one of two sets of baud rates to be generated by the

BRG (see Table 5).

The selected set of rates is available for use by the Channel A and

B receivers and transmitters as described in CSRA and CSRB.

Baud rate generator characteristics are given in Table 6.

Table 7. ACR 6:4 Field Definition

ACR

6:4

MODE CLOCK SOURCE

000 Counter External (IP2)

001 Counter TxCA – 1X clock of Channel A

transmitter

010 Counter TxCB – 1X clock of Channel B

transmitter

011 Counter Crystal or external clock

(X1/CLK) divided by 16

100 Timer (square wave) External (IP2)

101 Timer (square wave) External (IP2) divided by 16

110 Timer (square wave) Crystal or external clock

(X1/CLK)

111 Timer (square wave) Crystal or external clock

(X1/CLK) divided by 16

NOTE: The timer mode generates a squarewave.

ACR[6:4] – Counter/Timer Mode And Clock Source Select

This field selects the operating mode of the counter/timer and its

clock source as shown in Table 7.

ACR[3:0] – IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable

This field selects which bits of the input port change register (IPCR)

cause the input change bit in the interrupt status register (ISR[7]) to

be set. If a bit is in the ‘on’ state the setting of the corresponding bit

in the IPCR will also result in the setting of ISR[7], which results in

the generation of an interrupt output if IMR[7] = 1. If a bit is in the

‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7].

IPCR – Input Port Change Register

IPCR[7:4] – IP3, IP2, IP1, IP0 Change-of-State

These bits are set when a change-of-state, as defined in the input

port section of this data sheet, occurs at the respective input pins.

They are cleared when the IPCR is read by the CPU. A read of the

IPCR also clears ISR[7], the input change bit in the interrupt status

an interrupt to the CPU.

IPCR[3:0] – IP3, IP2, IP1, IP0 Change-of-State

These bits provide the current state of the respective inputs. The

information is unlatched and reflects the state of the input pins at the

time the IPCR is read.

ISR – Interrupt Status Register

This register provides the status of all potential interrupt sources.

The contents of this register are masked by the Interrupt Mask

in the IMR is also a ‘1’, the INTRN output will be asserted (Low). If

the corresponding bit in the IMR is a zero, the state of the bit in the

ISR has no effect on the INTRN output. Note that the IMR does not

mask the reading of the ISR – the true status will be provided

regardless of the contents of the IMR. The contents of this register

are initialized to H‘00’

when the DUART is reset.

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SC26C92C1A,512

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UART Interface IC UART DUAL W/FIFO

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