SC26C92C1A,512 Datasheet SC26C92C1A,518, SC26C92A1B,557, SC26C92C1B,551 | P7-P9

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

AC CHARACTERISTICS

= 5V ± 10%, T

= –40_C to 85_C, unless otherwise specified.

LIMITS

SYMBOL PARAMETER Min Typ

Max UNIT

Reset Timing (See Figure 3)

RES

RESET pulse width 200 ns

Bus Timing

(See Figure 4)

A0-A3 setup time to RDN, WRN Low 10 ns

A0-A3 hold time from RDN, WRN Low 25 ns

CEN setup time to RDN, WRN Low 0 ns

CEN hold time from RDN, WRN High 0 ns

WRN, RDN pulse width 70 ns

Data valid after RDN Low 55 ns

Data bus floating after RDN High 25 ns

Data setup time before WRN or CEN High 25 ns

Data hold time after WRN or CEN High 0 ns

RWD

High time between reads and/or writes

30 ns

Port Timing

(See Figure 5)

Port input setup time before RDN Low 0 ns

Port input hold time after RDN High 0 ns

output valid from WRN High 100 ns

Interrupt Timing (See Figure 6)

INTRN (or OP3-OP7 when used as interrupts) negated from:

Read RxFIFO (RxRDY/FFULL interrupt) 100 ns

Write TxFIFO (TxRDY interrupt) 100 ns

Reset command (break change interrupt) 100 ns

Stop C/T command (counter interrupt) 100 ns

Read IPCR (input port change interrupt) 100 ns

Write IMR (clear of interrupt mask bit) 100 ns

Clock Timing (See Figure 7)

CLK

X1/CLK High or Low time 50 ns

CLK

X1/CLK frequency 0.1 3.6864 8 MHz

CTC

CTCLK (IP2) High or Low time 55 ns

CTC

CTCLK (IP2) frequency 0 8 MHz

RxC High or Low time (16X) 30 ns

RxC frequency (16X)

(1X)

MHz

TxC High or Low time (16X) 30 ns

TxC frequency (16X)

(1X)

MHz

Transmitter Timing (See Figure 8)

TXD

TxD output delay from TxC external clock input on IP pin 60 ns

TCS

Output delay from TxC low at OP pin to TxD data output 5 30 ns

Receiver Timing (See Figure 9)

RXS

RxD data setup time before RxC high at external clock input on IP pin 50 ns

RXH

RxD data hold time after RxC high at external clock input on IP pin 50 ns

NOTES:

1. Parameters are valid over specified temperature range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5ns

maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and

output voltages of 0.8V and 2.0V, as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C

= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C

= 50pF, R

= 2.7KΩ to V

5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and

WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.

6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must

be negated for t

RWD

to guarantee that any status register changes are valid.

7. Minimum frequencies are not tested but are guaranteed by design. Crystal frequencies 2 to 4 MHz.

8. Clocks for 1X mode should be symmetrical.

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

Block Diagram

The SC26C92 DUART consists of the following eight major sections:

data bus buffer, operation control, interrupt control, timing,

communications Channels A and B, input port and output port.

Refer to the Block Diagram.

Data Bus Buffer

The data bus buffer provides the interface between the external and

internal data buses. It is controlled by the operation control block to

allow read and write operations to take place between the controlling

CPU and the DUART.

Operation Control

The operation control logic receives operation commands from the

CPU and generates appropriate signals to internal sections to

control device operation. It contains address decoding and read and

write circuits to permit communications with the microprocessor via

the data bus.

Interrupt Control

A single active-Low interrupt output (INTRN) is provided which is

activated upon the occurrence of any of eight internal events.

Associated with the interrupt system are the Interrupt Mask Register

(IMR) and the Interrupt Status Register (ISR). The IMR can be

programmed to select only certain conditions to cause INTRN to be

asserted. The ISR can be read by the CPU to determine all

currently active interrupting conditions.

Outputs OP3-OP7 can be programmed to provide discrete interrupt

outputs for the transmitter, receivers, and counter/timer.

When OP3 to OP7 are programmed as interrupts, their output

buffers are changed to the open drain active low configuration.

These pins may be used for DMA and modem control.

TIMING CIRCUITS

Crystal Clock

The timing block consists of a crystal oscillator, a baud rate

generator, a programmable 16-bit counter/timer, and four clock

selectors. The crystal oscillator operates directly from a crystal

connected across the X1/CLK and X2 inputs. If an external clock of

the appropriate frequency is available, it may be connected to

X1/CLK. The clock serves as the basic timing reference for the

Baud Rate Generator (BRG), the counter/timer, and other internal

circuits. A clock signal within the limits specified in the

specifications section of this data sheet must always be supplied to

the DUART.

If an external is used instead of a crystal, X1 should be driven using

a configuration similar to the one in Figure 7.

BRG

The baud rate generator operates from the oscillator or external

clock input and is capable of generating 27 commonly used data

communications baud rates ranging from 50 to 38.4K baud.

Programming bit 0 of MR0 to a “1” gives additional baud rates to

230.4kB. These will be in the 16X mode. A 3.6864MHz crystal or

external clock must be used to get the standard baud rates. The

clock outputs from the BRG are at 16X the actual baud rate. The

counter/timer can be used as a timer to produce a 16X clock for any

other baud rate by counting down the crystal clock or an external

clock. The four clock selectors allow the independent selection, for

each receiver and transmitter, of any of these baud rates or external

timing signal.

Counter–Timer

The Counter/Timer is a programmable 16–bit divider that is used for

generating miscellaneous clocks or generating timeout periods.

These clocks may be used by any or all of the receivers and trans-

mitters in the DUART or may be directed to an I/O pin for miscella-

neous use.

Counter/Timer programming

The counter timer is a 16–bit programmable divider that operates in

one of three modes: counter, timer, and time out.

• Timer mode generates a square wave.

• Counter mode generates a time delay.

• Time out mode counts time between received characters.

The C/T uses the numbers loaded into the Counter/Timer Lower

its divisor. The counter timer is controlled with six commands: Start/

Stop C/T, Read/Write Counter/Timer lower register and Read/Write

Counter/Timer upper register. These commands have slight differ-

ences depending on the mode of operation. Please see the detail of

the commands under the CTPL/CTPU register descriptions.

Baud Rate Generation with the C/T

When the timer is selected as baud rates for receiver or transmitter

via the Clock Select register their output will be configured as a 16x

clock. Therefore one needs to program the timer to generate a

clock 16 times faster than the data rate. The formula for calculating

’n’, the number loaded to the CTPU and CTPL registers, based on a

particular input clock frequency is shown below.

For the timer mode the formula is as follows:

Clockinputfrequency

2 16 Baudratedesired

NOTE: ‘n’ may not assume values of 0 and 1.

The frequency generated from the above formula will be at a rate 16

times faster than the desired baud rate. The transmitter and receiv-

er state machines include divide by 16 circuits, which provide the

final frequency and provide various timing edges used in the qualify-

ing the serial data bit stream. Often this division will result in a non–

integer value: 26.3 for example. One may only program integer

numbers to a digital divider. There for 26 would be chosen. If 26.7

were the result of the division then 27 would be chosen. This gives

a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage

error of 1.14% or 1.12% respectively, well within the ability of the

asynchronous mode of operation. Higher input frequency to the

counter reduces the error effect of the fractional division

One should be cautious about the assumed benign effects of small

errors since the other receiver or transmitter with which one is com-

municating may also have a small error in the precise baud rate. In

a ”clean” communications environment using one start bit, eight data

bits and one stop bit the total difference allowed between the trans-

mitter and receiver frequency is approximately 4.6%. Less than

eight data bits will increase this percentage.

Communications Channels A and B

Each communications channel of the SC26C92 comprises a

full-duplex asynchronous receiver/transmitter (UART). The

Philips Semiconductors Product specification

SC26C92

Dual universal asynchronous receiver/transmitter (DUART)

2000 Jan 31

operating frequency for each receiver and transmitter can be

selected independently from the baud rate generator, the

counter/timer, or from an external input.

The transmitter accepts parallel data from the CPU, converts it to a

serial bit stream, inserts the appropriate start, stop, and optional

parity bits and outputs a composite serial stream of data on the TxD

output pin.

The receiver accepts serial data on the RxD pin, converts this serial

input to parallel format, checks for start bit, stop bit, parity bit (if any),

or break condition and sends an assembled character to the CPU

via the receive FIFO. Three status bits (Break Received, Framing

and Parity Errors) are also FIFOed with each data character.

Input Port

The inputs to this unlatched 7-bit port can be read by the CPU by

performing a read operation at address H’D’. A High input results in

a logic 1 while a Low input results in a logic 0. D7 will always read

as a logic 1. The pins of this port can also serve as auxiliary inputs

to certain portions of the DUART logic or modem and DMA control.

Four change-of-state detectors are provided which are associated

with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High

transition of these inputs, lasting longer than 25 - 50µs, will set the

corresponding bit in the input port change register. The bits are

cleared when the register is read by the CPU. Any change-of-state

can also be programmed to generate an interrupt to the CPU.

The input port pulse detection circuitry uses a 38.4KHz sampling

clock derived from one of the baud rate generator taps. This results

in a sampling period of slightly more than 25µs (this assumes that

the clock input is 3.6864MHz). The detection circuitry, in order to

guarantee that a true change in level has occurred, requires two

successive samples at the new logic level be observed. As a

consequence, the minimum duration of the signal change is 25µs if

the transition occurs “coincident with the first sample pulse”. The

50µs time refers to the situation in which the change-of-state is “just

missed” and the first change-of-state is not detected until 25µs later.

All the IP pins have a small pull-up device that will source 1 to 4 mA

of current from V

. These pins do not require pull-up devices or

connections if they are not used.

Output Port

The output ports are controlled from five places: the OPCR register,

SOPR, ROPR, the MR registers and the command register (CR).

The OPCR register controls the source of the data for the output

ports OP2 through OP7. The data source for output ports OP0 and

OP1 is controlled by the MR and CR registers. Normally the data

source for the OP pins is from the OPR register. The OP pin drive

the inverted level (complement) of the OPR register. Example:

when the SOPR is used to set the OPR bit to a logical 1 then the

associated OP pin will drive a logical 0.

The content of the OPR register is controlled by the “Set Output Port

Bits Command” and the “Reset Output Bits Command”. These com-

mands are at E and F, respectively. When these commands are

used, action takes place only at the bit locations where ones exist.

For example, a one in bit location 5 of the data word used with the

“Set Output Port Bits” command will result in OPR(5) being set to

one. The OP5 would then be set to zero (V

SS ). Similarly, a one in

bit position 5 of the data word associated with the “Reset Output

Ports Bits” command would set OPR(5) to zero and, hence, the pin

OP5 to a one (Vdd).

Please note that these pins drive both high and low. However when

they are programmed to represent interrupt type functions (such as

RxRDY) they will be switched to an open drain configuration. In this

configuration an external pull–up device will be required

OPERATION

Transmitter

The SC26C92 is conditioned to transmit data when the transmitter is

enabled through the command register. The SC26C92 indicates to

the CPU that it is ready to accept a character by setting the TxRDY

bit in the status register. This condition can be programmed to

generate an interrupt request at OP0, OP1 and INTRN. When the

transmitter is initially enabled the TxRDY and TxEMT bits will be set

in the status register. When a character is loaded to the transmit

FIFO the TxEMT bit will be reset. The TxEMT will not set until: 1)

the transmit FIFO is empty and the transmit shift register has

finished transmitting the stop bit of the last character written to the

transmit FIFO, or 2) the transmitter is disabled and then re–enabled.

The TxRDY bit is set whenever the transmitter is enabled and the

TxFIFO is not full. Data is transferred from the holding register to

transmit shift register when it is idle or has completed transmission

of the previous character. Characters cannot be loaded into the

TxFIFO while the transmitter is disabled.

The transmitter converts the parallel data from the CPU to a serial

bit stream on the TxD output pin. It automatically sends a start bit

followed by the programmed number of data bits, an optional parity

bit, and the programmed number of stop bits. The least significant

bit is sent first. Following the transmission of the stop bits, if a new

character is not available in the TxFIFO, the TxD output remains

High and the TxEMT bit in the Status Register (SR) will be set to 1.

Transmission resumes and the TxEMT bit is cleared when the CPU

loads a new character into the TxFIFO.

If the transmitter is disabled, it continues operating until the charac-

ter currently being transmitted and any characters in the TxFIFO

including parity and stop bit(s) have been completed.

Note the differences between the transmitter disable and the trans-

mitter reset: reset stops all transmission immediately, effectively

clears the TxFIFO and resets all status and Tx interrupt conditions.

Transmitter disable clears all Tx status and interrupts BUT allows

the Tx to complete the transmission of all data in the TxFIFO and in

the shift register. While the Tx is disabled the TxFIFO can not be

loaded with data.

The transmitter can be forced to send a continuous Low condition by

issuing a send break command from the command register. The

transmitter output is returned to the normal high with a stop break

command.

The transmitter can be reset through a software command. If it is

reset, operation ceases immediately and the transmitter must be

enabled through the command register before resuming operation.

If the CTS option is enabled (MR2[4] = 1), the CTSN input at IP0 or

IP1 must be low in order for the character to be transmitted. The

transmitter will check the state of the CTS input at the beginning of

each character transmitted. If it is found to be High, the transmitter

will delay the transmission of any following characters until the CTS

has returned to the low state. CTS going high during the serializa-

tion of a character will not affect that character.

Transmitter “RS485 turnaround”

The transmitter can also control the RTSN outputs, OP0 or OP1 via

MR2[5]. When this mode of operation is set, the meaning of the

OP0 and OP1 signal will usually be ‘end of message’. See

description of the MR2[5] bit for more detail.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

SC26C92C1A,512

Mfr. #:

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Manufacturer:

NXP Semiconductors

Description:

UART Interface IC UART DUAL W/FIFO

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SC26C92C1A,512

SC26C92C1A,512

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